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    Single layer capacitor with dissimilar metallizations
    93.
    发明授权
    Single layer capacitor with dissimilar metallizations 有权
    具有不同金属化的单层电容器

    公开(公告)号：US06917509B1

    公开(公告)日：2005-07-12

    申请号：US10301335

    申请日：2002-11-21

    Applicant: Daniel F. Devoe ,  Lambert Devoe ,  Alan D. Devoe

    Inventor： Daniel F. Devoe ,  Lambert Devoe ,  Alan D. Devoe

    IPC: H01G2/06 ,  H01G4/228 ,  H05K3/32 ,  H05K3/34 ,  H01G4/008 ,  H01G4/06

    CPC classification number: H01G4/228 ,  H01G2/065 ,  H01L2224/48091 ,  H01L2924/19107 ,  H05K3/328 ,  H05K3/341 ,  H05K2201/10643 ,  H05K2201/10659 ,  H05K2201/10909 ,  H05K2203/049 ,  H01L2924/00014

    Abstract: A single layer ceramic capacitor for wire bonding or solder or epoxy attachment wherein a bottom metallization is of a lesser purity than a top metallization whereby the bottom metallization may be effectively soldered without leaching of the metal and the top metallization may be wire bonded. In an exemplary embodiment, the top metallization is essentially pure gold and the bottom metallization is an alloy of gold and platinum and/or palladium. The top and bottom metallizations are provided on a dielectric body that advantageously comprises a ceramic having a sintering temperature below the melting point of gold. In a further exemplary embodiment, the capacitance of the capacitor may be enhanced by providing one or more interior metallization planes parallel to the exterior metallizations and connected thereto by conductive vias.

    Abstract translation: 用于引线接合或焊料或环氧树脂附着的单层陶瓷电容器，其中底部金属化的纯度比顶部金属化的纯度低，由此底部金属化可以有效地焊接而不会浸出金属，并且顶部金属化可以是引线键合的。 在示例性实施例中，顶部金属化基本上是纯金，底部金属化是金和铂和/或钯的合金。 顶部和底部金属化物提供在电介质体上，其有利地包括具有低于金熔点的烧结温度的陶瓷。 在另一示例性实施例中，可以通过提供一个或多个内部金属化平面平行于外部金属化并通过导电通孔与其连接的电容来增强电容器的电容。

    Ball grid array package with external leads
    95.
    发明申请
    Ball grid array package with external leads 审中-公开
    具有外部引线的球栅阵列封装

    公开(公告)号：US20050077610A1

    公开(公告)日：2005-04-14

    申请号：US10680099

    申请日：2003-10-08

    Applicant: Tzyy Tan ,  Suet Woon ,  Say Tan

    Inventor： Tzyy Tan ,  Suet Woon ,  Say Tan

    IPC: H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H05K3/34 ,  H01L23/48

    CPC classification number: H01L23/495 ,  H01L23/3128 ,  H01L23/49816 ,  H01L2924/0002 ,  H01L2924/1433 ,  H05K3/341 ,  H05K3/3415 ,  H05K3/3421 ,  H05K3/3436 ,  H05K3/3447 ,  H05K2201/10659 ,  H05K2201/10734 ,  Y02P70/613 ,  H01L2924/00

    Abstract: In some embodiments, a package suitable to contain one or more semiconductor dies includes one or more solder-balls at an underside of said package and one or more external leads at a side edge of said package. Any or all of the solder-balls and external leads may serve as external electrical terminations of the package. The external leads may be surface mount leads and/or through-hole leads. In some embodiments, a printed circuit board may include pads designed to be soldered to solder-balls of a package and pads designed to be soldered to external leads of the package.

    Abstract translation: 在一些实施例中，适于容纳一个或多个半导体管芯的封装在所述封装的下侧包括一个或多个焊球，以及在所述封装的侧边缘处的一个或多个外部引线。 任何或全部焊球和外部引线可用作封装的外部电气终端。 外部引线可以是表面贴装引线和/或通孔引线。 在一些实施例中，印刷电路板可以包括设计成焊接到封装的焊球的焊盘和设计成焊接到封装的外部引线的焊盘。

    Electronic module having canopy-type carriers
    98.
    发明申请
    Electronic module having canopy-type carriers 审中-公开

    公开(公告)号：US20030137808A1

    公开(公告)日：2003-07-24

    申请号：US10341522

    申请日：2003-01-13

    Inventor： Kenneth J. Kledzik ,  Jason C. Engle

    IPC: H05K007/20

    CPC classification number: H05K1/141 ,  H01L25/105 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/0002 ,  H05K1/0231 ,  H05K3/0061 ,  H05K3/3405 ,  H05K3/3421 ,  H05K3/368 ,  H05K2201/049 ,  H05K2201/1034 ,  H05K2201/10515 ,  H05K2201/10659 ,  H05K2201/10689 ,  H05K2201/10734 ,  H05K2201/10924 ,  H01L2924/00

    Abstract: An improved multi-chip module includes a main circuit board having an array of electrical interconnection pads to which are mounted a plurality of IC package units. Each IC package unit includes a pair of IC packages, both of which are mounted on opposite sides of a package carrier. The package units may be mounted on one or both sides of the main circuit board. A first primary embodiment of the invention employs a laminar package carrier having a pair of major planar surfaces. Each planar surface incorporates electrical contact pads. One IC package is surface mounted on each major planar surface, by interconnecting the leads of the package with the contact pads on the planar surface, to form the IC package unit. A second primary embodiment of the invention utilizes a carrier substrate, which has a pair of recesses for back-to-back surface mounting of the IC package pair. The two IC packages may be in contact with opposite sides of a heat sink layer embedded within the carrier substrate. Each resulting IC package unit is surface mounted to the main circuit board. A third primary embodiment of the invention incorporates features of both the first and second primary embodiments. One of the packages is mounted on a planar surface of the carrier right side up, while the other package is mounted on the carrier in a recess upside down. Several variants of this embodiment are possible. Either the IC package that is mounted on the planar surface of the carrier, or the IC package that is mounted within the recess, may be mounted adjacent to the main circuit board. In the former case, the adjacent package of the package unit fits within a recess on the main circuit board. In the latter case, the adjacent package of the package unit mounts on a planar surface of the main circuit board. For any of the three primary main embodiments, the carrier may be equipped with its own set of interconnection leads which interface with the interconnection pads on the main circuit board or connection may be made directly between the leads of one package and the interconnection pads of the circuit board.

    Circuit housing clamp and method of manufacture therefor
    99.
    发明授权
    Circuit housing clamp and method of manufacture therefor 失效
    印刷电路板外壳夹

    公开(公告)号：US06586684B2

    公开(公告)日：2003-07-01

    申请号：US09896409

    申请日：2001-06-29

    Applicant: Kristopher Frutschy ,  Glenn E. Stewart ,  Farzaneh Yahyaei-Moayyed ,  Geoffery L. Reid

    Inventor： Kristopher Frutschy ,  Glenn E. Stewart ,  Farzaneh Yahyaei-Moayyed ,  Geoffery L. Reid

    IPC: H05K116

    CPC classification number: H05K1/0263 ,  H01L23/49811 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K3/325 ,  H05K7/1092 ,  H05K2201/10325 ,  H05K2201/10393 ,  H05K2201/10659 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y10T29/4913

    Abstract: An electronic assembly includes one or more conductive clamps (302, 304, FIG. 3), which are used to supply current to an integrated circuit (IC) package (308). The conductive clamps are attached to a printed circuit (PC) board (312), which supplies the current to the IC package over one clamp, and receives returned current from the IC package over another clamp. Each clamp contacts a contact pad (330) on the surface of the PC board, and contacts another contact pad (334) on the top surface of the IC package. Vias (338, 339) and conductive planes (340, 342) within the package then carry current to and from an IC (e.g., IC 306) connected to the package. In another embodiment, the clamp (904, FIG. 9) holds a conductive structure (902) in place between the PC board contact pad (908) and the IC package contact pad (914), and current is carried primarily over the conductive structure, rather than over the clamp.

    Abstract translation: 电子组件包括用于向集成电路（IC）封装（308）提供电流的一个或多个导电钳位件（302,304，图3）。 导电夹具连接到印刷电路板（PC）（312），该印刷电路板（312）通过一个夹具将电流提供给IC封装，并且通过另一个夹具接收来自IC封装的返回电流。 每个夹具接触PC板表面上的接触焊盘（330），并接触IC封装顶表面上的另一接触焊盘（334）。 封装内的通孔（338,339）和导电平面（340,342）然后将电流传送到连接到封装的IC（例如，IC 306）。 在另一个实施例中，夹具（904，图9）将导电结构（902）保持在PC板接触焊盘（908）和IC封装接触焊盘（914）之间的适当位置，电流主要承载在导电结构 ，而不是超过钳位。

    Electronic package having multiple-zone interconnects and methods of manufacture
    100.
    发明申请
    Electronic package having multiple-zone interconnects and methods of manufacture 有权
    具有多区域互连的电子封装和制造方法

    公开(公告)号：US20030103338A1

    公开(公告)日：2003-06-05

    申请号：US10004002

    申请日：2001-11-30

    Applicant: Intel Corporation

    Inventor： Gilroy J. Vandentop ,  Yuan-Liang Li

    IPC: H05K007/10 ,  H05K007/12

    CPC classification number: H01L24/73 ,  H01L23/49827 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/30107 ,  H01L2924/351 ,  H05K3/3436 ,  H05K2201/10378 ,  H05K2201/10659 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49169 ,  H01L2924/00

    Abstract: To accommodate thermal stresses arising from different coefficients of thermal expansion (CTE) of a packaged or unpackaged die and a substrate, the package incorporates two or more different interconnect zones. A first interconnect zone, located in a central region of the die, employs a relatively stiff interconnect structure. A second interconnect zone, located near the periphery of the die, employs a relatively compliant interconnect structure. Additional interconnect zones, situated between the first and second interconnect zones and having interconnect structure with compliance qualities intermediate those of the first and second zones, can optionally be employed. In one embodiment, solder connections providing low electrical resistance are used in the first interconnect zone, and compliant connections, such as nanosprings, are used in the second interconnect zone. Methods of fabrication, as well as application of the package to an electronic assembly, an electronic system, and a data processing system are also described.

    Abstract translation: 为了适应由封装的或未封装的裸片和衬底的不同热膨胀系数（CTE）产生的热应力，封装包含两个或多个不同的互连区域。 位于模具的中心区域中的第一互连区域采用相对较硬的互连结构。 位于模具周边附近的第二互连区采用相对顺应的互连结构。 位于第一和第二互连区之间并具有与第一和第二区之间的顺应性质量的互连结构的附加互连区可以任选地被采用。 在一个实施例中，在第一互连区域中使用提供低电阻的焊接连接，并且在第二互连区域中使用诸如纳米脉冲的顺应连接。 还描述了制造方法以及将包装应用于电子组件，电子系统和数据处理系统。

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