公开(公告)号：US20170110439A1

公开(公告)日：2017-04-20

申请号：US14970558

申请日：2015-12-16

申请人： Powertech Technology Inc.

发明人： Chia-Hsiang Yuan ,  Chia-Wei Chang ,  Kuo-Ting Lin ,  Yong-Cheng Chuang

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L24/03 ,  H01L24/06 ,  H01L24/20 ,  H01L24/45 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/06505 ,  H01L2224/12105 ,  H01L2224/214 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92224 ,  H01L2225/06506 ,  H01L2225/06562 ,  H01L2225/1035 ,  H01L2225/1058

摘要： Provided is a package structure including a substrate, N dies, N first pads, N vertical wires, and a second pad. The N dies are stacked alternatively on the substrate, so as to form a multi-die stack structure. The N dies include, from bottom to top, first to Nth dies, wherein N is an integer greater than 1. The first die is a bottom die, and the Nth die is a top die. The first pads are disposed on an active surface of the dies respectively. The vertical wires are disposed on the first pads respectively. The second pad is disposed on the top die.

公开(公告)号：US09627360B2

公开(公告)日：2017-04-18

申请号：US15262304

申请日：2016-09-12

申请人： Samsung Electronics Co., Ltd.

发明人： Sang-Guk Han ,  Seok-Joon Moon ,  Beom-jun Jin

IPC分类号： G01R31/00 ,  H01L25/065 ,  H05K1/11 ,  H05K1/18 ,  H01L21/66 ,  H01L23/00 ,  G11C5/06

CPC分类号： H01L25/0657 ,  G01R31/2808 ,  G01R31/2818 ,  G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C29/04 ,  G11C29/12 ,  G11C29/56 ,  G11C29/56016 ,  G11C2029/5602 ,  H01L22/30 ,  H01L22/32 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/538 ,  H01L24/09 ,  H01L24/48 ,  H01L24/49 ,  H01L24/80 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/0912 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4912 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01068 ,  H01L2924/181 ,  H05K1/0268 ,  H05K1/111 ,  H05K1/117 ,  H05K1/181 ,  H05K3/002 ,  H05K3/245 ,  H05K3/28 ,  H05K3/288 ,  H05K3/323 ,  H05K2201/0187 ,  H05K2201/035 ,  H05K2201/09036 ,  H05K2201/09472 ,  H05K2201/099 ,  H05K2201/10159 ,  H05K2203/162 ,  Y10T29/49117 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An electronic device having a printed circuit board is provided. In one embodiment, the printed circuit board includes a plurality of external pads to be coupled with an external device and a plurality of bypass pads for testing an electric circuit. The external pads are exposed and at least one of the plurality of bypass pads are not exposed from an outer surface of the PCB. A system using the electronic device and a method of testing an electronic device are also provided.

公开(公告)号：US09627327B2

公开(公告)日：2017-04-18

申请号：US14815937

申请日：2015-07-31

申请人： Samsung Electronics Co., Ltd.

发明人： Baik-woo Lee ,  Dong-hun Lee ,  Jae-gwon Jang ,  Chul-yong Jang

IPC分类号： H01L21/00 ,  H01L23/552 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  B29C70/78 ,  B29K63/00 ,  B29L9/00 ,  B29L31/34 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L23/552 ,  B29C70/78 ,  B29K2063/00 ,  B29L2009/005 ,  B29L2031/3481 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/85

摘要： Provided is a method of manufacturing a semiconductor package. The method includes mounting a semiconductor device on a substrate; disposing a mold on the substrate, wherein the mold is formed to cover the semiconductor device such that at least one inner side surface of the mold has a slope; providing a molding material into the mold to encapsulate the semiconductor device; removing the mold from the substrate; and forming an electromagnetic shielding (EMS) layer to cover a top surface and side surfaces of the molding material.

公开(公告)号：US20170092622A1

公开(公告)日：2017-03-30

申请号：US15372392

申请日：2016-12-07

申请人： Shenzhen Huiding Technology Co., Ltd.

发明人： Baoquan WU ,  Wei LONG

IPC分类号： H01L25/065 ,  H01L23/48

CPC分类号： H01L25/0657 ,  G06K9/0002 ,  G06K9/0053 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/24 ,  H01L24/73 ,  H01L24/82 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/071 ,  H01L25/105 ,  H01L25/112 ,  H01L25/16 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/24147 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06558 ,  H01L2924/15153 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2924/00

摘要： The present disclosure discloses a chip packaging module, including: a first chip, where a first pad is disposed on a side neighboring to a front surface of the first chip; at least a second chip, where at least one second chip is disposed on a rear side of the first chip, each second chip has a second pad, and wherein the first pad of the first chip is connected to the second pad of the second chip via a redistribution layer. According to the chip packaging module in the present disclosure, a second chip is disposed on a rear side of a first chip, and a first pad is connected to a second pad via a redistribution layer. By means of a redistribution technology on surfaces of multiple chips, a lead of a pad on a front surface of a fingerprint recognition chip is masterly winded to the back for interconnection, so that an induction area on the front surface of the chip can fully contact with a human body. In addition, the multi-chip redistribution technology can also greatly narrow down an interconnection distance between chips, which improves efficiency of communication between chips.

公开(公告)号：US09601467B1

公开(公告)日：2017-03-21

申请号：US14845150

申请日：2015-09-03

申请人： Invensas Corporation

发明人： Cyprian Emeka Uzoh ,  Rajesh Katkar

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L27/14634 ,  H01L21/568 ,  H01L23/3114 ,  H01L24/09 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/46 ,  H01L24/48 ,  H01L24/49 ,  H01L24/82 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L27/14618 ,  H01L27/14636 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/09181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48101 ,  H01L2224/48227 ,  H01L2224/4903 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/143 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： In a microelectronic package, a first wire bond wire is coupled to an upper surface of a substrate. A first bond mass is coupled to another end of the first wire bond wire. A second wire bond wire is coupled to the upper surface. A second bond mass is coupled to another end of the second wire bond wire. The first and second wire bond wires laterally jut out horizontally away from the upper surface of the substrate for at least a distance of approximately 2 to 3 times a diameter of both the first wire bond wire and the second wire bond wire. The first wire bond wire and the second wire bond wire are horizontal for the distance with respect to being co-planar with the upper surface within +/−10 degrees.

公开(公告)号：US09599516B2

公开(公告)日：2017-03-21

申请号：US14499629

申请日：2014-09-29

申请人： Samsung Electronics Co., Ltd.

发明人： EungChang Lee

IPC分类号： H01L23/48 ,  G01K7/16 ,  H01L25/18 ,  G11C7/04 ,  G01K7/02 ,  G01L1/22 ,  H01L25/10 ,  H01L21/66 ,  G11C5/04 ,  G01B7/16 ,  H01L23/31 ,  H01L23/58 ,  H01L23/00 ,  H01L25/065

CPC分类号： G01K7/16 ,  G01B7/20 ,  G01K7/02 ,  G01L1/2293 ,  G11C5/04 ,  G11C7/04 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/585 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/06135 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/06596 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1441 ,  H01L2924/1443 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

摘要： A semiconductor package includes a package substrate having first connecting pads and second connecting pads, and a semiconductor chip mounted on the package substrate. The semiconductor chip includes a semiconductor device comprising a semiconductor substrate and electrically connected to input/output (I/O) pads, and a measuring device formed on the semiconductor device and electrically connected to measuring pads. The I/O pads are electrically connected to the first connecting pads, and the measuring pads are electrically connected to the second connecting pads.

公开(公告)号：US09589930B2

公开(公告)日：2017-03-07

申请号：US14588243

申请日：2014-12-31

申请人： Chul Park ,  Kilsoo Kim ,  In Lee

发明人： Chul Park ,  Kilsoo Kim ,  In Lee

IPC分类号： H01L25/065

CPC分类号： H01L25/0652 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48147 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/85399

摘要： A semiconductor package comprises a package substrate; a first chip stack and a second chip stack mounted side by side on the package substrate, wherein the first and second chip stacks each include a plurality of semiconductor chips stacked on the package substrate, wherein each of the semiconductor chips includes a plurality of bonding pads provided on a respective edge region thereof, wherein at least some of the plurality of bonding pads are functional pads, and wherein the functional pads occupy a region that is substantially less than an entirety of the respective edge region.

摘要翻译： 半导体封装包括封装衬底; 第一芯片堆叠和第二芯片堆叠并排安装在封装基板上，其中第一和第二芯片堆叠各自包括堆叠在封装衬底上的多个半导体芯片，其中每个半导体芯片包括多个焊盘 设置在其相应的边缘区域上，其中所述多个接合焊盘中的至少一些是功能焊盘，并且其中所述功能焊盘占据实质上小于所述相应边缘区域整体的区域。

公开(公告)号：US20170047305A1

公开(公告)日：2017-02-16

申请号：US15228859

申请日：2016-08-04

申请人： Marvell World Trade Ltd.

发明人： Chenglin Liu ,  Shiann-Ming Liou

IPC分类号： H01L23/00

CPC分类号： H01L24/32 ,  G06F13/38 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/85399

摘要： Embodiments provide a packaging arrangement that comprises a package substrate. A random access memory die is coupled to the package substrate and a serializing random access memory interface die coupled to (i) the package substrate and (ii) the random access memory die.

摘要翻译： 实施例提供了包括封装衬底的封装装置。 随机存取存储器管芯耦合到封装衬底，并且串联随机存取存储器接口管芯耦合到（i）封装衬底和（ii）随机存取存储器管芯。

公开(公告)号：US20170033087A1

公开(公告)日：2017-02-02

申请号：US15224490

申请日：2016-07-29

申请人： Samsung Electronics Co., Ltd.

发明人： Zhengrong CHEN

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/92 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/06135 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/85005 ,  H01L2224/92163 ,  H01L2225/06506 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/45099

摘要： A stack semiconductor package structure includes a substrate; a second chip comprising a plurality of conductive bumps formed on a surface thereof; and a first chip positioned on the second chip, wherein the second chip is electrically connected to the substrate through the plurality of conductive bumps in a flip-chip manner, and wherein the first chip is electrically connected to the second chip through a plurality of bonding wires.

摘要翻译： 堆叠半导体封装结构包括衬底; 第二芯片，其包括形成在其表面上的多个导电凸块; 以及位于所述第二芯片上的第一芯片，其中所述第二芯片以倒装芯片的方式通过所述多个导电凸块电连接到所述基板，并且其中所述第一芯片通过多个键合电连接到所述第二芯片 电线

公开(公告)号：US09559079B2

公开(公告)日：2017-01-31

申请号：US14638741

申请日：2015-03-04

申请人： SK hynix Inc.

发明人： Moon Soo Kim

IPC分类号： H01L23/498 ,  H01L25/065

CPC分类号： H01L25/0652 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2924/15184 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor stack package includes a printed circuit board (PCB), a first semiconductor chip, and a second semiconductor chip. The first and second semiconductor chips are disposed side-by-side on a first surface of the PCB to be spaced apart from each other. Each of the first and second semiconductor chips includes a command/address (CA) chip pad and a data input/output (DQ) chip pad. The CA chip pad of the first semiconductor chip is electrically coupled to the CA chip pad of the second semiconductor chip through a CA bonding wire.

摘要翻译： 半导体堆叠封装包括印刷电路板（PCB），第一半导体芯片和第二半导体芯片。 第一和第二半导体芯片并排布置在PCB的第一表面上以彼此间隔开。 第一和第二半导体芯片中的每一个包括命令/地址（CA）芯片焊盘和数据输入/输出（DQ）芯片焊盘。 第一半导体芯片的CA芯片焊盘通过CA键合线电耦合到第二半导体芯片的CA芯片焊盘。