公开(公告)号：US20110192885A1

公开(公告)日：2011-08-11

申请号：US12977913

申请日：2010-12-23

Applicant: Hendrik Pieter HOCHSTENBACH ,  Willem Dirk van DRIEL ,  Eric OOMS

Inventor： Hendrik Pieter HOCHSTENBACH ,  Willem Dirk van DRIEL ,  Eric OOMS

IPC: B23K31/02 ,  B23K1/20

CPC classification number: H01L24/85 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/45015 ,  H01L2224/45147 ,  H01L2224/4807 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48507 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/78301 ,  H01L2224/85045 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/85365 ,  H01L2224/85948 ,  H01L2924/00015 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/10157 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/20757 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/45144

Abstract: Consistent with an example embodiment, a wirebonding process comprises forming a bond pad with a roughened upper surface, lowering a copper wirebond ball onto the roughened bond bad, and applying a force to the wirebond ball against the roughened surface, A heat treatment is applied to form the bond between the wirebond ball and the roughened surface, wherein the bond is formed without use of ultrasonic energy.This process avoids the use of ultrasonic welding and thereby reduces the occurrence of microcracks and resulting Chip Out of the Bond (COUB) and Metal Peel Off (MPO) failures. The roughened surface of the bond pad improves the reliability of the connection.

Abstract translation: 与示例性实施例一致，引线接合工艺包括形成具有粗糙化的上表面的接合焊盘，将铜线焊球降低到粗糙的焊接不良上，并且向引线焊球施加力以抵抗粗糙表面。将热处理应用于 形成引线球和粗糙表面之间的结合，其中，不使用超声波能量形成结合。 该过程避免了使用超声波焊接，从而减少了微裂纹的发生，从而减少了Bond（COUB）和Metal Peel Off（MPO）故障中的芯片。 接合焊盘的粗糙表面提高了连接的可靠性。

公开(公告)号：US07975901B2

公开(公告)日：2011-07-12

申请号：US12794911

申请日：2010-06-07

Applicant: Toru Maeda ,  Tetsuya Utano ,  Akinobu Teramoto

Inventor： Toru Maeda ,  Tetsuya Utano ,  Akinobu Teramoto

IPC: B23K31/02 ,  B23K37/00 ,  C23F1/00

CPC classification number: H01L24/85 ,  B23K20/007 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/78268 ,  H01L2224/78301 ,  H01L2224/7865 ,  H01L2224/85009 ,  H01L2224/85013 ,  H01L2224/85045 ,  H01L2224/85065 ,  H01L2224/85075 ,  H01L2224/85181 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01018 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/00014 ,  H01L2924/01001 ,  H01L2924/00

Abstract: A bonding apparatus including a chamber for maintaining an inert gas atmosphere; a first plasma torch for performing a surface treatment on pads and electrodes, the first plasma torch being attached in the chamber, to apply gas plasma to a substrate and a semiconductor chip that is placed inside the chamber; a second plasma torch for performing a surface treatment on an initial ball and/or wire at a tip end of a capillary that is positioned inside the chamber, the second plasma torch being attached in the chamber, to apply gas plasma to the initial ball and/or wire; and a bonding unit for bonding the surface-treated initial ball and/or wire to the surface-treated pads and electrodes in the chamber, thereby cleaning of the surface of the electrodes and pads as well as the wire can be effectively performed.

Abstract translation: 一种接合装置，包括用于维持惰性气体气氛的室; 用于对焊盘和电极执行表面处理的第一等离子体焰炬，第一等离子体焰炬附接在腔室中，以将气体等离子体施加到衬底和放置在腔室内的半导体芯片; 第二等离子体焰炬，用于对位于所述腔室内的毛细管的前端处的初始球和/或线进行表面处理，所述第二等离子体焰炬附接在所述腔室中，以将气体等离子体施加到所述初始球体;以及 /或电线; 以及用于将表面处理的初始球和/或线结合到腔室中的表面处理的垫和电极的接合单元，从而可以有效地执行电极和垫的表面以及线的清洁。

公开(公告)号：US20110151622A1

公开(公告)日：2011-06-23

申请号：US12929160

申请日：2011-01-05

Applicant: Akira Oga

Inventor： Akira Oga

IPC: H01L21/603

CPC classification number: H01L24/85 ,  H01L23/4952 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/48247 ,  H01L2224/4845 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/48599 ,  H01L2224/4911 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/49425 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/85045 ,  H01L2224/85051 ,  H01L2224/85181 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85947 ,  H01L2224/85951 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/4554 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: The present invention provides a method of manufacturing a semiconductor device in which a plurality of wires are connected to the same electrode on a semiconductor chip, the method making it possible to inhibit an increase in electrode area. First, ball bonding is performed to compressively bond a first ball to an electrode on a semiconductor chip to form a first connection portion. Wedge bonding is then performed on an inner lead. Subsequently, ball bonding is performed to compress a second ball against the first connection portion from immediately above to bond the second ball to form a second connection portion. Wedge bonding is then performed on the inner lead.

Abstract translation: 本发明提供一种制造半导体器件的方法，其中多个导线连接到半导体芯片上的相同电极，该方法使得可以抑制电极面积的增加。 首先，进行球接合以将第一球压缩接合到半导体芯片上的电极，以形成第一连接部分。 然后在内引线上进行楔形粘结。 随后，执行球接合以从紧接在上方压紧第二连接部分上的第二球，以将第二球接合以形成第二连接部。 然后在内引线上进行楔形接合。

公开(公告)号：US07955904B2

公开(公告)日：2011-06-07

申请号：US12844644

申请日：2010-07-27

Applicant: David J. K. Meadowcroft

Inventor： David J. K. Meadowcroft

IPC: H01L21/00

CPC classification number: H01S5/02248 ,  G02B6/4201 ,  G02B6/4246 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/85 ,  H01L2224/48091 ,  H01L2224/484 ,  H01L2224/4899 ,  H01L2224/49175 ,  H01L2224/78 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/181 ,  H01L2924/3025 ,  H01S5/005 ,  H01S5/183 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

Abstract: A wirebond protector has an elongated shape that corresponds to the elongated array of wirebonds along the edge of a microelectronic device that connect a semiconductor die to electrical conductors on a substrate. In making the microelectronic device with wirebond protection, wirebonds are first formed in the conventional manner The wirebond protector is then attached to the device in an orientation in which it extends along the array of wirebonds to at least partially cover the wirebonds.

公开(公告)号：US20110108959A1

公开(公告)日：2011-05-12

申请号：US13007743

申请日：2011-01-17

Applicant: David R. Hembree

Inventor： David R. Hembree

IPC: H01L23/48 ,  H01L21/44 ,  H01L21/50

CPC classification number: H01L25/0657 ,  B23K20/004 ,  B23K20/005 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L24/81 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/45565 ,  H01L2224/45644 ,  H01L2224/4807 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48145 ,  H01L2224/48455 ,  H01L2224/48471 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/48992 ,  H01L2224/78301 ,  H01L2224/8121 ,  H01L2224/81224 ,  H01L2224/81815 ,  H01L2224/85043 ,  H01L2224/85045 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/85951 ,  H01L2224/9202 ,  H01L2225/06506 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/20751 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/30105 ,  H01L2924/3025 ,  H05K3/4046 ,  H05K2201/10287 ,  H05K2203/049 ,  Y10T29/49117 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49162 ,  Y10T29/49169 ,  Y10T29/53213 ,  H01L2924/20752 ,  H01L2924/00 ,  H01L2924/2075 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on the back side, forming a bonded contact on the wire on the circuit side, and then severing the wire from the bonded contact. The through wire interconnect includes the wire in the via, the contact on the back side and the bonded contact on the circuit side. The contact on the back side, and the bonded contact on the circuit side, permit multiple components to be stacked with electrical connections between adjacent components. A system for performing the method includes the substrate with the via, and a wire bonder having a bonding capillary configured to thread the wire through the via, and form the contact and the bonded contact. The semiconductor component can be used to form chip scale components, wafer scale components, stacked components, or interconnect components for electrically engaging or testing other semiconductor components.

Abstract translation: 用于通过导线互连制造半导体部件的方法包括提供具有电路侧，背面和通孔的基板的步骤。 该方法还包括以下步骤：将导线穿过通孔，在背面的导线上形成接触，在电路侧的导线上形成接合接触，然后将线从接合接触件断开。 通线互连包括通孔中的导线，背侧的触点和电路侧的接合触点。 背面的触点和电路侧的接合触点允许多个部件与相邻部件之间的电连接层叠。 用于执行该方法的系统包括具有通孔的基板和具有接合毛细管的引线接合器，所述接合毛细管被配置为使线穿过通孔，并形成接触和接合接触。 半导体部件可用于形成用于电接合或测试其它半导体部件的芯片级部件，晶片级部件，堆叠部件或互连部件。

公开(公告)号：US07939928B2

公开(公告)日：2011-05-10

申请号：US12731420

申请日：2010-03-25

Applicant: James Zaccardi

Inventor： James Zaccardi

IPC: H01L23/522

CPC classification number: H01L25/50 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06136 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/4556 ,  H01L2224/45565 ,  H01L2224/45599 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/8385 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10161 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/07025 ,  H01L2924/0635 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor package has a substrate with a plurality of contact pads. A first semiconductor die is mounted to the substrate. First bond wires are formed between each of the center-row contact pads of the first semiconductor die and the substrate contact pads. The first bond wires include an electrically insulative coating formed over the shaft that covers a portion of a surface of a bumped end of the first bond wires. An epoxy material is deposited over the first semiconductor die. A second semiconductor die is mounted to the epoxy material. Second bond wires are formed between each of the center-row contact pads of the second semiconductor die and the substrate contact pads. The second bond wires include an electrically insulative coating formed over the shaft of the second bond wires that covers a portion of a surface of a bumped end of the second bond wires.

Abstract translation: 半导体封装具有带有多个接触焊盘的衬底。 第一半导体管芯安装在基板上。 第一接合线形成在第一半导体管芯的每个中心排接触焊盘和衬底接触焊盘之间。 第一接合线包括形成在轴上的电绝缘涂层，其覆盖第一接合线的凸起端的表面的一部分。 环氧树脂材料沉积在第一半导体管芯上。 第二半导体管芯安装在环氧树脂材料上。 第二接合线形成在第二半导体管芯的每个中心排接触焊盘和衬底接触焊盘之间。 第二接合线包括形成在第二接合线的轴上的电绝缘涂层，其覆盖第二接合线的凸起端的一部分表面。

公开(公告)号：US20110101487A1

公开(公告)日：2011-05-05

申请号：US12985567

申请日：2011-01-06

Applicant: Kyounghwan Kim ,  Hongkook Min ,  Sungkyoo Park

Inventor： Kyounghwan Kim ,  Hongkook Min ,  Sungkyoo Park

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L24/85 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05624 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/48475 ,  H01L2224/48479 ,  H01L2224/48624 ,  H01L2224/48799 ,  H01L2224/85051 ,  H01L2224/85201 ,  H01L2224/859 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01059 ,  H01L2924/01066 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2224/48824 ,  H01L2924/00 ,  H01L2224/4554

Abstract: A circuit under pad structure includes a substrate, a pad electrode, wiring layers interlayer insulation layers alternately disposed between the pad electrode and the substrate, and at least one circuit pattern integral with the substrate, disposed beneath the lowermost wiring layer and spanned by the pad electrode. The width of each wiring layer is smaller than the width of the wiring layer beneath it, i.e., closer to the substrate. The structure is fabricated such that it resists cracking, which maximizes its production yield, and possesses a minimal footprint.

Abstract translation: 衬垫结构下的电路包括衬底，焊盘电极，交替地设置在焊盘电极和衬底之间的布线层层间绝缘层，以及与衬底一体的至少一个电路图案，设置在最下面的布线层的下方并被衬垫 电极。 每个布线层的宽度小于其下面的布线层的宽度，即更靠近基片。 该结构被制造成使得其抵抗裂纹，其最大化其产量，并且具有最小的占地面积。

公开(公告)号：US07932131B2

公开(公告)日：2011-04-26

申请号：US11983041

申请日：2007-11-05

Applicant: Sally Foong ,  Kevin Guan ,  Changhak Lee ,  Lai Nguk Chin ,  Royce Yeoh Kao Tziat ,  Foong Yue Ho

Inventor： Sally Foong ,  Kevin Guan ,  Changhak Lee ,  Lai Nguk Chin ,  Royce Yeoh Kao Tziat ,  Foong Yue Ho

IPC: H01L21/00 ,  H01L23/02 ,  H01L23/52

CPC classification number: H01L23/49575 ,  H01L24/27 ,  H01L24/29 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L2224/29007 ,  H01L2224/29012 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29288 ,  H01L2224/29339 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/78 ,  H01L2224/83194 ,  H01L2224/8385 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/078 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/48237 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A method and structure for reducing the size of semiconductor package is disclosed. In one example embodiment, a method for stacking dies of a semiconductor package includes forming a set of insulated bonding wires between respective bonding pads of a first semiconductor integrated circuit die and a conductive layer electrically detached from the respective bonding pads, applying an adhesive material on a top surface of the first semiconductor integrated circuit die, and securing a second semiconductor integrated circuit die one the top surface of the first semiconductor integrated circuit die with the adhesive material.

Abstract translation: 公开了一种减小半导体封装尺寸的方法和结构。 在一个示例性实施例中，一种用于堆叠半导体封装的管芯的方法包括在第一半导体集成电路管芯的相应接合焊盘与从各个焊盘电气分离的导电层之间形成一组绝缘接合线，将粘合材料施加在 第一半导体集成电路管芯的顶表面，并用第一半导体集成电路将第一半导体集成电路管芯的顶表面与粘合剂材料固定。

公开(公告)号：US20110058979A1

公开(公告)日：2011-03-10

申请号：US12740588

申请日：2008-09-11

Applicant: Hiroshi Murai ,  Jun Chiba ,  Fujio Amada

Inventor： Hiroshi Murai ,  Jun Chiba ,  Fujio Amada

IPC: C22C5/02

CPC classification number: C22C5/02 ,  B23K35/3013 ,  H01L24/02 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/43 ,  H01L2224/45015 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45164 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/78301 ,  H01L2224/78303 ,  H01L2224/78306 ,  H01L2224/85045 ,  H01L2224/85181 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85439 ,  H01L2224/859 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01021 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/0106 ,  H01L2924/0107 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01105 ,  H01L2924/01204 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/01071 ,  H01L2924/00014 ,  H01L2924/01201 ,  H01L2924/01202 ,  H01L2924/01203 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/013 ,  H01L2924/20752 ,  H01L2924/00013 ,  H01L2924/01006

Abstract: [Issues to be Solved] Second bonding failures caused by attached oxide of additive elements on high purity Au bonding wire are to be resolved.[Solution Means] Au alloy bonding wires comprising: 5-100 wt ppm Mg, 5-20 wt ppm In, 5-20 wt ppm Al, 5-20 wt ppm Yb, and residual Au of 99.995 wt % purity or higher, and adding 5-20 wt ppm Ca, and for these alloys adding at least one element among 5-20 wt ppm La, 5-20 wt ppm Lu, 5-100 wt ppm Sn, 5-100 wt ppm Sr to the alloy, and/or, moreover, adding 0.01-1.2 wt % Pd to these alloys. Bonding wire, which contains these trace additive elements do not cause a disturbance by accumulated contamination, because of contamination, which formed at ball formation by micro discharge and at the first bonding on the tip of the capillary, transferring to the wire at second bonding.

Abstract translation: [待解决的问题]解决了在高纯度Au接合线上附加元素的附着氧化物引起的第二次接合故障。 [解决方案]包括：5-100重量ppm的Mg，5-20重量ppm的In，5-20重量ppm的Al，5-20重量ppm的Yb和99.995重量％的纯度或更高的残余金，以及 添加5-20重量ppm的Ca，对于这些合金，在5-20重量ppm的La，5-20重量ppm的Lu，5-100重量ppm的Sn，5-100重量ppm的Sr中加入至少一种元素，并且 /或此外，向这些合金中添加0.01-1.2重量％的Pd。 含有这些微量添加元素的粘合线不会由于污染而引起累积污染的干扰，这是由于通过微量放电在第一次接合而形成的污染，并且在第二次接合时转移到导线。

公开(公告)号：US07888802B2

公开(公告)日：2011-02-15

申请号：US12608018

申请日：2009-10-29

Applicant: Kyoung-Hwan Kim

Inventor： Kyoung-Hwan Kim

IPC: H01L23/488

CPC classification number: H01L24/05 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05624 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/4847 ,  H01L2224/48475 ,  H01L2224/48624 ,  H01L2224/48799 ,  H01L2224/85051 ,  H01L2224/85201 ,  H01L2224/859 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/48824 ,  H01L2924/00

Abstract: A bonding pad structure of a semiconductor device and a method of manufacturing the same reduce the likelihood of peel-off defects from occurring. The bonding pad structure includes a substrate, an interlayer insulation layer on the substrate, an upper wiring layer on the interlayer insulation layer, and a plurality of lower wiring layers disposed in the interlayer insulation layer between the upper wiring layer and the substrate and configured to prevent the interlayer insulation layer from cracking especially during a wire bonding process in which a wire is bonded to the upper wiring layer. For example, the respective areas occupied by the lower wiring layers sequentially increase in the interlayer insulation layer in a downward direction from the upper wiring layer towards the substrate. Also, each of the lower wiring layers may project further inwardly toward a central part of the bonding pad than the lower layer of wiring disposed above it in the interlayer insulation layer.

Abstract translation: 半导体器件的焊盘结构及其制造方法降低了剥离缺陷的发生的可能性。 焊盘结构包括基板，基板上的层间绝缘层，层间绝缘层上的上布线层以及设置在上布线层和基板之间的层间绝缘层中的多个下布线层， 防止层间绝缘层特别是在导线接合到上布线层的引线接合工艺期间发生龟裂。 例如，下层布线层所占据的各个区域在上层布线层朝向基板的向下方向上依次增加层间绝缘层。 此外，每个下布线层可以比在布置在层间绝缘层中的布线下层的布线的下层向内朝向接合焊盘的中心部分突出。