公开(公告)号：US20040099999A1

公开(公告)日：2004-05-27

申请号：US10651367

申请日：2003-08-29

Inventor： William J. Borland

IPC: B28B001/00 ,  C04B033/32 ,  H01G004/06 ,  H05K003/30

CPC classification number: H01G4/01 ,  H05K1/092 ,  H05K1/162 ,  H05K3/429 ,  H05K3/4611 ,  H05K3/4623 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09718 ,  H05K2201/09763 ,  Y10T29/4913

Abstract: A capacitor structure is fabricated by forming a pattern of first dielectrics over a foil, forming first electrodes over the first dielectrics, and co-firing the first dielectrics and the first electrodes. Co-firing of the dielectrics and the electrodes alleviates cracking caused by differences in thermal coefficient of expansion (TCE) between the electrodes and the dielectrics. Co-firing also ensures a strong bond between the dielectrics and the electrodes. In addition, co-firing allows multi-layer capacitor structures to be constructed, and allows the capacitor electrodes to be formed from copper.

Abstract translation: 通过在箔上形成第一电介质的图案来形成电容器结构，在第一电介质上形成第一电极，并共烧第一电介质和第一电极。 电介质和电极的共烧可减轻由电极和电介质之间的热膨胀系数（TCE）的差异引起的开裂。 共烧也确保电介质和电极之间的牢固结合。 另外，共烧允许构造多层电容器结构，并且允许电容器电极由铜形成。

公开(公告)号：US06507497B2

公开(公告)日：2003-01-14

申请号：US09848801

申请日：2001-05-04

Applicant: Naohiro Mashino

Inventor： Naohiro Mashino

IPC: H05K706

CPC classification number: H01L23/642 ,  H01L21/486 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15788 ,  H05K1/141 ,  H05K1/162 ,  H05K3/42 ,  H05K2201/09763 ,  H05K2201/09809 ,  H05K2201/10734 ,  Y10T29/4913 ,  Y10T29/49155

Abstract: An interposer adapted to be used between a mounting board and a semiconductor chip which is to be mounted on the mounting board. The interposer having a heat-resistant insulator having first and second surfaces, the insulator being provided with a plurality of through-holes opened at the first and second surfaces; wiring patterns formed on the first and second surfaces of the insulator electrically connected to each other by means of a conductor provided on an inner wall of at least one of the through-holes; and a capacitor. The capacitor has first electrode formed on the insulator and having a connecting portion formed on an inner wall of at least one of the other through-holes, a dielectric layer formed on the first electrode, and a second electrode formed on the dielectric layer.

Abstract translation: 适于在安装板和要安装在安装板上的半导体芯片之间使用的插入器。 所述插入器具有具有第一表面和第二表面的耐热绝缘体，所述绝缘体设置有在所述第一表面和所述第二表面处开口的多个通孔; 通过设置在至少一个通孔的内壁上的导体彼此电连接的绝缘体的第一和第二表面上形成的布线图案; 和电容器。 电容器具有形成在绝缘体上的第一电极，并且具有形成在至少一个其它通孔的内壁上的连接部分，形成在第一电极上的电介质层和形成在电介质层上的第二电极。

公开(公告)号：US6411194B2

公开(公告)日：2002-06-25

申请号：US79459601

申请日：2001-02-27

Applicant: VICTOR COMPANY OF JAPAN

Inventor： SHINDOH MOTOSHI ,  SEGAWA KEIJI ,  OTSUKI MITSURU

IPC: H01C17/12 ,  H05K1/02 ,  H05K1/16 ,  H05K3/38 ,  H05K3/46 ,  H01C1/012

CPC classification number: H05K1/167 ,  H01C17/12 ,  H05K1/0206 ,  H05K1/165 ,  H05K3/388 ,  H05K3/4644 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/0317 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2203/0361 ,  Y10T29/49082

Abstract: The invention provides a production method capable of forming a thin film resistance element having a thickness and a shape controlled in a high accuracy in a printed circuit board. The production method of a thin film resistance element formed on a printed circuit board, has the steps of forming a thin film resistance layer having a predetermined thickness on the printed circuit board through an insulation layer by a dry process used in producing a semiconductor, forming an electrically conductive layer on the thin resistance layer, and etching the electrically conductive layer selectively so as to make, at least, a pair of electrically conductive pads, resulting in the thin film resistance element having a predetermined value of resistivity between the pair of electrically conductive pads. Thereby, it is possible to form the thin film resistance element having a thickness and a shape controlled in a high accuracy on the printed circuit board.

Abstract translation: 本发明提供一种能够形成在印刷电路板中具有高精度的厚度和形状的薄膜电阻元件的制造方法。 形成在印刷电路板上的薄膜电阻元件的制造方法具有以下步骤：通过用于制造半导体的干法在印刷电路板上形成具有预定厚度的薄膜电阻层，形成 在所述薄电阻层上的导电层，并且选择性地蚀刻所述导电层，以便至少形成一对导电焊盘，导致所述薄膜电阻元件在所述一对电学上具有预定的电阻率值 导电垫。 因此，可以在印刷电路板上形成具有高精度的厚度和形状的薄膜电阻元件。

公开(公告)号：US06323096B1

公开(公告)日：2001-11-27

申请号：US09162800

申请日：1998-09-29

Applicant: Richard Joseph Saia ,  Kevin Matthew Durocher ,  Herbert Stanley Cole

Inventor： Richard Joseph Saia ,  Kevin Matthew Durocher ,  Herbert Stanley Cole

IPC: H01L2170

CPC classification number: H01L23/5389 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/5385 ,  H01L24/19 ,  H01L24/82 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01051 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K1/162 ,  H05K1/167 ,  H05K3/388 ,  H05K3/4076 ,  H05K3/426 ,  H05K3/4644 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2203/0315 ,  H05K2203/0361 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method for fabricating a flexible interconnect film includes applying a resistor layer over one or both surfaces of a dielectric film; applying a metallization layer over the resistor layer with the resistor layer including a material facilitating adhesion of the dielectric film and the metallization layer; applying a capacitor dielectric layer over the metallization layer; and applying a capacitor electrode layer over the capacitor dielectric layer. The capacitor electrode layer is patterned to form a first capacitor electrode; the capacitor dielectric layer is patterned; the metallization layer is patterned to form a resistor; and the metallization layer and the resistor layer are patterned to form an inductor and a second capacitor electrode. In one embodiment, the dielectric film includes a polyimide, the resistor layer includes tantalum nitride, and the capacitor dielectric layer includes amorphous hydrogenated carbon or tantalum oxide. If the resistor and metallization layers are applied over both surfaces of the dielectric film, passive components can be fabricated on both surfaces of the dielectric film. The dielectric film can have vias therein with the resistor and metallization layers extending through the vias. A circuit chip can be attached and coupled to the passive components by metallization patterned through vias in an additional dielectric layer.

Abstract translation: 制造柔性互连膜的方法包括在电介质膜的一个或两个表面上施加电阻层; 在所述电阻层上施加金属化层，所述电阻层包括促进所述电介质膜和所述金属化层的粘附的材料; 在所述金属化层上施加电容器电介质层; 以及在电容器电介质层上施加电容器电极层。 将电容器电极层图案化以形成第一电容器电极; 对电容器电介质层进行图案化; 图案化金属化层以形成电阻器; 并且金属化层和电阻层被图案化以形成电感器和第二电容器电极。 在一个实施例中，电介质膜包括聚酰亚胺，电阻层包括氮化钽，电容器介电层包括无定形氢化碳或氧化钽。 如果将电阻和金属化层施加在电介质膜的两个表面上，则可以在电介质膜的两个表面上制造无源元件。 电介质膜可以具有通孔，其中电阻器和金属化层延伸穿过通孔。 电路芯片可以通过在附加电介质层中通过通孔图案化的金属化而附接并耦合到无源部件。

公开(公告)号：US06278356B1

公开(公告)日：2001-08-21

申请号：US09572142

申请日：2000-05-17

Applicant: Wen-Yen Lin ,  Lin-Yeh Chen ,  Chin-Chi Chang ,  Shih-Ting Huang

Inventor： Wen-Yen Lin ,  Lin-Yeh Chen ,  Chin-Chi Chang ,  Shih-Ting Huang

IPC: H01L1012

CPC classification number: H05K1/167 ,  H05K1/095 ,  H05K1/162 ,  H05K3/064 ,  H05K2201/09763 ,  H05K2201/10045

Abstract: A flat, built-in resistor and capacitor has a substrate (10) made of dielectric material; a copper layer (12) formed on each surface of the substrate (10) and having an etched image (30) formed in each of the copper layers (12); a dielectric material layer (40) printed onto the copper layer (12) and filling up the etched image; and a resistance layer (50) printed onto the copper layer (12) and the dielectric material layer (40).

Abstract translation: 扁平的内置电阻器和电容器具有由电介质材料制成的衬底（10）; 形成在所述基板（10）的每个表面上并具有形成在每个所述铜层（12）中的蚀刻图像（30）的铜层（12）。 印刷在所述铜层（12）上并填充所述蚀刻图像的介电材料层（40）; 和印刷在铜层（12）和电介质材料层（40）上的电阻层（50）。

公开(公告)号：US5912507A

公开(公告)日：1999-06-15

申请号：US18363

申请日：1998-02-04

Applicant: Gregory J. Dunn ,  Lawrence E. Lach ,  Daniel R. Gamota

Inventor： Gregory J. Dunn ,  Lawrence E. Lach ,  Daniel R. Gamota

IPC: H01L23/498 ,  H05K1/09 ,  H05K1/16 ,  H05K3/34 ,  H01L23/48

CPC classification number: H01L23/49811 ,  H05K1/167 ,  H01L2224/16225 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K1/095 ,  H05K2201/09481 ,  H05K2201/09763 ,  H05K2201/10734 ,  H05K3/3436

Abstract: A microelectronic assembly, such as a surface-mount device or a ball-grid array (BGA) package, has one or more integral resistors. The integral resistors are incorporated into one or more of the microelectronic assembly's electrical leads or connections. The integral resistors preferably terminate in a solderable pad. For example, the BGA package may include an IC chip and interposer. A terminal is located on a surface of the IC chip, on a surface of the interposer, or on the surface of the substrate to which the BGA is mounted. An electrically-resistive material overlies the terminal and electrically couples the terminal to a bond pad, thereby defining an integral resistor. The integral resistors reduce electrical resonances and reflections that may otherwise degrade the signal integrity and reliability of the electrical system employing the device; hence, reduce or eliminate the requirement for discrete resistors for the microelectronic assembly.

Abstract translation: 诸如表面贴装器件或球栅阵列（BGA）封装的微电子组件具有一个或多个积分电阻器。 集成电阻器被并入到微电子组件的电引线或连接中的一个或多个中。 整体电阻器优选地终止于可焊接焊盘中。 例如，BGA封装可以包括IC芯片和插入器。 端子位于IC芯片的表面上，在中介层的表面上，或位于安装有BGA的基板的表面上。 电阻材料覆盖在端子上并将端子电耦合到接合焊盘，从而限定一个整体电阻器。 积分电阻减少电共振和反射，否则可能会降低采用该器件的电气系统的信号完整性和可靠性; 因此，减少或消除了对于微电子组件的分立电阻器的要求。

公开(公告)号：US5876538A

公开(公告)日：1999-03-02

申请号：US805524

申请日：1997-02-26

Applicant: Klaus Steinle ,  Claudio De La Prieta ,  Manfred Moser ,  Annette Seibold

Inventor： Klaus Steinle ,  Claudio De La Prieta ,  Manfred Moser ,  Annette Seibold

IPC: H05K3/46 ,  H01L21/48 ,  H05K1/03 ,  H05K1/09 ,  H05K1/16 ,  B32B31/26 ,  H01G4/12 ,  H01G4/224

CPC classification number: H05K1/162 ,  H01L21/4857 ,  H01L21/4867 ,  H05K1/0306 ,  H05K1/092 ,  H05K2201/09763 ,  H05K3/4611 ,  H05K3/4629 ,  Y10T29/435

Abstract: Ceramic multilayer substrates as circuit supports for complex electronic circuits wth integrated capacitors are manufactured by printing capacitor structures, using the screen printing process, directly onto a first green ceramic film. The first green ceramic film with the printed structures is arranged in a stack with further green ceramic films, laminated, and fired. During lamination of the ceramic films, the printed structures are pressed into the ceramic films so that after firing, a multilayer substrate with integrated capacitors results.

Abstract translation: 作为集成电容器的复杂电子电路的电路支撑体的陶瓷多层基板通过使用丝网印刷工艺将电容器结构印刷在第一个绿色陶瓷膜上而制造。 具有印刷结构的第一个绿色陶瓷膜以更多的绿色陶瓷膜堆叠堆叠并层压并烧制。 在层压陶瓷膜期间，印刷结构被压入陶瓷膜中，使得在烧制之后，形成具有集成电容器的多层基板。

公开(公告)号：US5813881A

公开(公告)日：1998-09-29

申请号：US320086

申请日：1994-10-07

Applicant: Richard J. Nathan ,  James J. D. Lan ,  Steve S. Chiang

Inventor： Richard J. Nathan ,  James J. D. Lan ,  Steve S. Chiang

IPC: G01R1/04 ,  G01R1/06 ,  G01R31/28 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01R29/00 ,  H01R31/06 ,  H05K1/00 ,  H05K1/14 ,  H05K1/16 ,  H05K3/06 ,  H05K3/24 ,  H05K3/42 ,  H05K3/46 ,  H05K7/10

CPC classification number: G01R1/04 ,  H01L21/485 ,  H01L23/49827 ,  H01L23/5382 ,  H01R29/00 ,  H05K1/0293 ,  H05K7/1092 ,  G01R1/06 ,  G01R31/2863 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2924/13091 ,  H01R23/70 ,  H01R31/06 ,  H05K1/0289 ,  H05K1/029 ,  H05K1/0292 ,  H05K1/0298 ,  H05K1/141 ,  H05K1/167 ,  H05K2201/0305 ,  H05K2201/09763 ,  H05K2201/10181 ,  H05K2201/10212 ,  H05K2201/10689 ,  H05K2203/0542 ,  H05K2203/105 ,  H05K2203/1115 ,  H05K2203/173 ,  H05K2203/175 ,  H05K3/062 ,  H05K3/243 ,  H05K3/429 ,  H05K3/4611

Abstract: Two types of programmable elements, fuses and antifuses, are disclosed for forming an electrically programmable cable in one embodiment and a cable adapter in another embodiment. The cable and the cable adapter can be used for interconnecting a cable connector of a first configuration to a cable connector of a second configuration.

Abstract translation: 公开了两种可编程元件，熔丝和反熔丝，用于在一个实施例中形成电可编程电缆，在另一实施例中用于电缆适配器。 电缆和电缆适配器可用于将第一配置的电缆连接器与第二配置的电缆连接器互连。

公开(公告)号：US4858064A

公开(公告)日：1989-08-15

申请号：US251747

申请日：1988-10-03

Applicant: Masao Segawa ,  Masayuki Arakawa

Inventor： Masao Segawa ,  Masayuki Arakawa

IPC: H01L23/66 ,  H01L25/16 ,  H05K1/03 ,  H05K1/09 ,  H05K1/16 ,  H05K3/34

CPC classification number: H05K1/162 ,  H01L23/66 ,  H01L25/16 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K1/092 ,  H05K1/16 ,  H05K2201/09763 ,  H05K2201/09809 ,  H05K3/3405

Abstract: A thick-film high frequency signal circuit apparatus with a feedthrough capacitor. The apparatus includes a thick-film circuit in which a high frequency signal circuit is constituted on a substrate in a thick-film configuration, a shielding case for housing the thick-film circuit therein, a feedthrough capacitor constituted on one surface of the substrate in the thick-film configuration and a terminal for transmitting signals between the thick-film circuit and a circuit outside the shielding case, the terminal having a first end coupled to the thick-film circuit through the feedthrough capacitor and a second end protruding outside the shielding case through a hole defined therein.

公开(公告)号：US4724040A

公开(公告)日：1988-02-09

申请号：US940733

申请日：1986-12-11

Applicant: Yamahiro Iwasa

Inventor： Yamahiro Iwasa

IPC: H05K1/09 ,  H05K1/16 ,  H05K3/46 ,  B23F1/02 ,  B44C1/22 ,  C03C15/00 ,  C03C25/06

CPC classification number: H05K1/162 ,  H05K3/4664 ,  H05K1/095 ,  H05K1/167 ,  H05K2201/0209 ,  H05K2201/0347 ,  H05K2201/09763 ,  H05K3/4685 ,  Y10T29/49099

Abstract: A method is described for producing multilayer circuits including a resistor circuit on one side of a copper laminated base board, wherein the base board is etched to provide a plurality of circuits of a first layer, effectively processed with a plating-resistant resist and an electrically conductive copper paste to form a plurality of circuits of a second layer, immersed in a metal plating solution to provide a metal plating layer on the copper paste to thereby form the circuits of the second layer on the circuits of the first layer, coated with an electrically conductive paste to provide a pair of electric terminals between two of the circuits of the second layer, and coated with an electrically resistant resist of a predetermined electric resistance value on a part extended between the two electric terminals.

Abstract translation: 描述了一种用于制造包括在铜层压基板的一侧上的电阻器电路的多层电路的方法，其中蚀刻基板以提供第一层的多个电路，有效地用耐电镀抗蚀剂和电 导电铜浆以形成第二层的多个电路，浸入金属电镀溶液中以在铜膏上提供金属镀层，从而在第一层的电路上形成第二层的电路，涂覆有 导电膏以在第二层的两个电路之间提供一对电端子，并且在两个电端子之间延伸的部分上涂覆有预定电阻值的电阻抗蚀剂。