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公开(公告)号：US20140027431A1
公开(公告)日：2014-01-30
申请号：US13559318
申请日：2012-07-26
Applicant: Ming-Da Cheng , Hsiu-Jen Lin , Cheng-Ting Chen , Wei-Yu Chen , Chien-Wei Lee , Chung-Shi Liu
Inventor： Ming-Da Cheng , Hsiu-Jen Lin , Cheng-Ting Chen , Wei-Yu Chen , Chien-Wei Lee , Chung-Shi Liu
CPC classification number: H05B3/02 , B23K3/087 , B23K2101/40 , H01L21/67721 , H01L21/6838 , H01L24/75 , H01L24/81 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/75744 , H01L2224/7598 , H01L2224/81191 , H01L2224/81815 , H01L2224/97 , H01L2924/3511 , H01L2924/37001 , Y10T29/41 , H01L2924/00014 , H01L2224/81 , H01L2924/014
Abstract: A method includes placing a first package component over a vacuum boat, wherein the vacuum boat comprises a hole, and wherein the first package component covers the hole. A second package component is placed over the first package component, wherein solder regions are disposed between the first and the second package components. The hole is vacuumed, wherein the first package component is pressed by a pressure against the vacuum boat, and wherein the pressure is generated by a vacuum in the hole. When the vacuum in the hole is maintained, the solder regions are reflowed to bond the second package component to the first package component.
Abstract translation: 一种方法包括将第一包装部件放置在真空舟皿上，其中真空舟皿包括孔，并且其中第一包装部件覆盖该孔。 第二包装部件放置在第一包装部件上，其中焊料区域设置在第一和第二包装部件之间。 该孔被抽真空，其中第一包装部件被压靠在真空舟皿上的压力，并且其中压力由孔中的真空产生。 当保持孔中的真空时，回流焊接区域以将第二包装部件结合到第一包装部件。
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12.发明申请SEMICONDUCTOR PACKAGE HAVING SOLDER JOINTED REGION WITH CONTROLLED AG CONTENT 审中-公开具有受控AG内容的焊接接头区域的半导体封装公开(公告)号：US20130099371A1
公开(公告)日：2013-04-25
申请号：US13278621
申请日：2011-10-21
Applicant: Ming-Da CHENG , Kuei-Wei HUANG , Yu-Peng TSAI , Cheng-Ting CHEN , Hsiu-Jen LIN , Chung-Shi LIU
Inventor： Ming-Da CHENG , Kuei-Wei HUANG , Yu-Peng TSAI , Cheng-Ting CHEN , Hsiu-Jen LIN , Chung-Shi LIU
IPC: H01L23/498 , H01L21/60
CPC classification number: H01L24/13 , H01L24/05 , H01L24/11 , H01L24/16 , H01L2224/0345 , H01L2224/0401 , H01L2224/05008 , H01L2224/05022 , H01L2224/05124 , H01L2224/05139 , H01L2224/05147 , H01L2224/05184 , H01L2224/05572 , H01L2224/05647 , H01L2224/05666 , H01L2224/05681 , H01L2224/05686 , H01L2224/1132 , H01L2224/1145 , H01L2224/11452 , H01L2224/1146 , H01L2224/11849 , H01L2224/13012 , H01L2224/13014 , H01L2224/13082 , H01L2224/13111 , H01L2224/13147 , H01L2224/16145 , H01L2224/16238 , H01L2224/81191 , H01L2924/00014 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/01029 , H01L2924/04941 , H01L2924/04953 , H01L2924/01013 , H01L2924/01024 , H01L2924/01028 , H01L2924/0105 , H01L2924/01079 , H01L2924/01073 , H01L2924/01049 , H01L2924/0103 , H01L2924/01025 , H01L2924/01022 , H01L2924/01047 , H01L2924/00012 , H01L2924/00 , H01L2224/05552
Abstract: A semiconductor package includes a workpiece with a conductive trace and a chip with a conductive pillar. The chip is attached to the workpiece and a solder joint region is formed between the conductive pillar and the conductive trace. The silver (Ag) content in the solder layer is between 0.5 and 1.8 weight percent.
Abstract translation: 半导体封装包括具有导电迹线的工件和具有导电柱的芯片。 芯片附着在工件上，并且在导电柱和导电迹线之间形成焊点区域。 焊料层中的银（Ag）含量为0.5-1.8重量％。
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公开(公告)号：US08235551B2
公开(公告)日：2012-08-07
申请号：US12634468
申请日：2009-12-09
Applicant: Jian-Shian Lin , Chieh-Lung Lai , Hsiu-Jen Lin , Weng-Jung Lu , Yi-Ping Huang , Ya-Chun Tu
Inventor： Jian-Shian Lin , Chieh-Lung Lai , Hsiu-Jen Lin , Weng-Jung Lu , Yi-Ping Huang , Ya-Chun Tu
CPC classification number: F21V19/02 , F21K9/00 , F21Y2107/50 , F21Y2115/10 , H01L25/0753 , H01L33/62 , H01L2224/29339 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2924/01047 , H01L2924/01322 , H01L2924/00014 , H01L2924/00 , H01L2924/01014
Abstract: A light-emitting diode (LED) module and an LED packaging method. As the LED module is packaged under the consideration of candela distribution, each of the lead frames of the LED chips packaged in the LED module is bended for tilting the LED chips by different angles to exhibit various lighting effects. Meanwhile, in the LED packaging method, a plurality of LED chips can be loaded on board rapidly and aligned by one operation to result in less deviation in the candela distribution curve.
Abstract translation: 一种发光二极管（LED）模块和一种LED封装方法。 由于LED模块在考虑到烛光分布的情况下被封装，所以封装在LED模块中的LED芯片的每个引线框架被弯曲以使LED芯片以不同的角度倾斜以呈现各种照明效果。 同时，在LED封装方法中，可以通过一次操作快速地将多个LED芯片加载在一起，从而导致烛光分布曲线的偏差较小。
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公开(公告)号：US20110127563A1
公开(公告)日：2011-06-02
申请号：US12854278
申请日：2010-08-11
Applicant: Hsiu Jen Lin , Jian Shian Lin , Shau Yi Chen , Chieh Lung Lai
Inventor： Hsiu Jen Lin , Jian Shian Lin , Shau Yi Chen , Chieh Lung Lai
CPC classification number: H01L23/53247 , H01L24/29 , H01L24/83 , H01L33/0079 , H01L33/0095 , H01L33/30 , H01L33/40 , H01L33/486 , H01L33/62 , H01L2224/29101 , H01L2224/29109 , H01L2224/29111 , H01L2224/83193 , H01L2224/83207 , H01L2224/8382 , H01L2224/83825 , H01L2224/8383 , H01L2224/83948 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/01327 , H01L2924/0133 , H01L2924/0134 , H01L2924/014 , H01L2924/09701 , H01L2924/12041 , H01L2924/12042 , H01L2924/15724 , H01L2924/15738 , H01L2924/15747 , H01L2924/1576 , H01L2924/15787 , H01L2924/351 , H01L2933/0066 , H01L2924/00 , H01L2924/01028 , H01L2924/01083 , H01L2924/00014
Abstract: A die-bonding method is suitable for die-bonding a LED chip having a first metal thin-film layer to a substrate. The method includes forming a second metal thin film layer on a surface of the substrate; forming a die-bonding material layer on the second metal thin film layer; placing the LED chip on the die-bonding material layer with the first metal thin film layer contacting the die-bonding material layer; heating the die-bonding material layer at a liquid-solid reaction temperature for a pre-curing time, so as to form a first intermetallic layer and a second intermetallic layer; and heating the die-bonding material layer at a solid-solid reaction temperature for a curing time, so as to perform a solid-solid reaction. The liquid-solid reaction temperature and the solid-solid reaction temperature are both lower than 110° C., and a melting point of the first and second intermetallic layers after the solid-solid reaction is higher than 200° C.
Abstract translation: 芯片接合方法适合于将具有第一金属薄膜层的LED芯片芯片接合到基板上。 该方法包括在基板的表面上形成第二金属薄膜层; 在所述第二金属薄膜层上形成芯片接合材料层; 将第一金属薄膜层与芯片接合材料层接触，将LED芯片放置在芯片接合材料层上; 在液固固体反应温度下加热芯片接合材料层预固化时间，以形成第一金属间层和第二金属间层; 并在固 - 固反应温度下加热芯片接合材料层达固化时间，以进行固 - 固反应。 液固反应温度和固 - 固反应温度均低于110℃，固 - 固反应后第一和第二金属间化合物的熔点高于200℃。
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公开(公告)号：US20100157595A1
公开(公告)日：2010-06-24
申请号：US12634468
申请日：2009-12-09
Applicant: Jian-Shian Lin , Chieh-Lung Lai , Hsiu-Jen Lin , Weng-Jung Lu , Yi-Ping Huang , Ya-Chun Tu
Inventor： Jian-Shian Lin , Chieh-Lung Lai , Hsiu-Jen Lin , Weng-Jung Lu , Yi-Ping Huang , Ya-Chun Tu
CPC classification number: F21V19/02 , F21K9/00 , F21Y2107/50 , F21Y2115/10 , H01L25/0753 , H01L33/62 , H01L2224/29339 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2924/01047 , H01L2924/01322 , H01L2924/00014 , H01L2924/00 , H01L2924/01014
Abstract: A light-emitting diode (LED) module and an LED packaging method. As the LED module is packaged under the consideration of candela distribution, each of the lead frames of the LED chips packaged in the LED module is bended for tilting the LED chips by different angles to exhibit various lighting effects. Meanwhile, in the LED packaging method, a plurality of LED chips can be loaded on board rapidly and aligned by one operation to result in less deviation in the candela distribution curve.
Abstract translation: 一种发光二极管（LED）模块和一种LED封装方法。 由于LED模块在考虑到烛光分布的情况下被封装，所以封装在LED模块中的LED芯片的每个引线框架被弯曲以使LED芯片以不同的角度倾斜以呈现各种照明效果。 同时，在LED封装方法中，可以通过一次操作快速地将多个LED芯片加载在一起，从而导致烛光分布曲线的偏差较小。
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Patent Agency Ranking
公开(公告)号：US20210263890A1
公开(公告)日：2021-08-26
申请号：US17248756
申请日：2021-02-05
Applicant: Hsiu-Jen Lin
Inventor： Hsiu-Jen Lin
Abstract: An intelligent storage system and an intelligent storage method thereof are disclosed. The system includes a cabinet and loading tables, each loading table includes an accommodating groove having a shape corresponding the shape of the object to be stored, and a sensing device in the accommodating groove. A central control device includes a processor electrically connected to the sensing device, the output device and an input device, and a system database for the processor to access or store information. The sensing devices senses whether there is a corresponding stored object in each accommodating groove to form a status signal carrying an identification code, and outputs it to the processor, then the processor accesses the corresponding information in the system database according to the identification code of the status signal, so as to realize the management and status display of the stored object, and effectively improve work safety and effectiveness.
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公开(公告)号：US09412717B2
公开(公告)日：2016-08-09
申请号：US13289719
申请日：2011-11-04
Applicant: Meng-Tse Chen , Hsiu-Jen Lin , Chun-Cheng Lin , Wen-Hsiung Lu , Ming-Da Cheng , Chung-Shi Liu
Inventor： Meng-Tse Chen , Hsiu-Jen Lin , Chun-Cheng Lin , Wen-Hsiung Lu , Ming-Da Cheng , Chung-Shi Liu
CPC classification number: H01L24/97 , B29C33/68 , B29C43/18 , H01L21/563 , H01L21/566 , H01L2224/16225 , H01L2924/01322 , H01L2924/181 , H01L2924/00
Abstract: Methods and apparatus for a forming molded underfills. A method is disclosed including loading a flip chip substrate into a selected one of the upper mold chase and lower mold chase of a mold press at a first temperature; positioning a molded underfill material in the at least one of the upper and lower mold chases while maintaining the first temperature which is lower than a melting temperature of the molded underfill material; forming a sealed mold cavity and creating a vacuum in the mold cavity; raising the temperature of the molded underfill material to a second temperature greater than the melting point to cause the molded underfill material to flow over the flip chip substrate forming an underfill layer and forming an overmolded layer; and cooling the flip chip substrate to a third temperature substantially lower than the melting temperature of the molded underfill material. An apparatus is disclosed.
Abstract translation: 用于成型模制底部填料的方法和装置。 公开了一种方法，其包括在第一温度下将倒装芯片衬底加载到模压机的上模追逐和下模追逐中的所选择的一个中; 将模制的底部填充材料定位在上模具和下模具中的至少一个中，同时保持低于模制的底部填充材料的熔融温度的第一温度; 形成密封的模腔并在模腔中产生真空; 将模制的底部填充材料的温度提高到大于熔点的第二温度，以使模制的底部填充材料在形成底部填充层的倒装芯片衬底上流动并形成包覆成型层; 并将所述倒装芯片基板冷却至基本上低于所述模制底部填充材料的熔融温度的第三温度。 公开了一种装置。
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公开(公告)号：US08884431B2
公开(公告)日：2014-11-11
申请号：US13228768
申请日：2011-09-09
Applicant: Chih-Wei Lin , Ming-Da Cheng , Wen-Hsiung Lu , Hsiu-Jen Lin , Bor-Ping Jang , Chung-Shi Liu , Mirng-Ji Lii , Chen-Hua Yu , Meng-Tse Chen , Chun-Cheng Lin , Yu-Peng Tsai , Kuei-Wei Huang , Wei-Hung Lin
Inventor： Chih-Wei Lin , Ming-Da Cheng , Wen-Hsiung Lu , Hsiu-Jen Lin , Bor-Ping Jang , Chung-Shi Liu , Mirng-Ji Lii , Chen-Hua Yu , Meng-Tse Chen , Chun-Cheng Lin , Yu-Peng Tsai , Kuei-Wei Huang , Wei-Hung Lin
IPC: H01L23/48 , H01L23/52 , H01L29/40 , H01L21/683 , H01L23/498 , H01L21/56 , H01L25/065 , H01L23/538 , H01L25/00 , H01L23/00 , H01L23/31 , H01L25/10 , H01L25/03 , H01L21/768
CPC classification number: H01L25/0657 , H01L21/52 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L21/76898 , H01L23/3128 , H01L23/3135 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/5389 , H01L24/03 , H01L24/05 , H01L24/09 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L24/92 , H01L24/97 , H01L25/03 , H01L25/0652 , H01L25/0655 , H01L25/105 , H01L25/50 , H01L2221/68331 , H01L2221/68345 , H01L2221/68377 , H01L2224/0231 , H01L2224/0401 , H01L2224/04105 , H01L2224/06515 , H01L2224/09181 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/16225 , H01L2224/16238 , H01L2224/73259 , H01L2224/81005 , H01L2224/81191 , H01L2224/81815 , H01L2224/9202 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06548 , H01L2924/14 , H01L2924/1461 , H01L2924/15192 , H01L2924/15311 , H01L2924/15321 , H01L2924/15322 , H01L2924/181 , H01L2924/19107 , H01L2924/00014 , H01L2224/81 , H01L2224/03 , H01L2924/014 , H01L2924/00
Abstract: Packaging methods and structures for semiconductor devices are disclosed. In one embodiment, a packaged semiconductor device includes a redistribution layer (RDL) having a first surface and a second surface opposite the first surface. At least one integrated circuit is coupled to the first surface of the RDL, and a plurality of metal bumps is coupled to the second surface of the RDL. A molding compound is disposed over the at least one integrated circuit and the first surface of the RDL.
Abstract translation: 公开了用于半导体器件的封装方法和结构。 在一个实施例中，封装的半导体器件包括具有第一表面和与第一表面相对的第二表面的再分配层（RDL）。 至少一个集成电路耦合到RDL的第一表面，并且多个金属凸块耦合到RDL的第二表面。 模制化合物设置在RDL的至少一个集成电路和第一表面上。
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公开(公告)号：US08716737B2
公开(公告)日：2014-05-06
申请号：US13530396
申请日：2012-06-22
Applicant: Hsiu Jen Lin , Jian Shian Lin , Shau Yi Chen , Chieh Lung Lai
Inventor： Hsiu Jen Lin , Jian Shian Lin , Shau Yi Chen , Chieh Lung Lai
CPC classification number: H01L23/53247 , H01L24/29 , H01L24/83 , H01L33/0079 , H01L33/0095 , H01L33/30 , H01L33/40 , H01L33/486 , H01L33/62 , H01L2224/29101 , H01L2224/29109 , H01L2224/29111 , H01L2224/83193 , H01L2224/83207 , H01L2224/8382 , H01L2224/83825 , H01L2224/8383 , H01L2224/83948 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/01327 , H01L2924/0133 , H01L2924/0134 , H01L2924/014 , H01L2924/09701 , H01L2924/12041 , H01L2924/12042 , H01L2924/15724 , H01L2924/15738 , H01L2924/15747 , H01L2924/1576 , H01L2924/15787 , H01L2924/351 , H01L2933/0066 , H01L2924/00 , H01L2924/01028 , H01L2924/01083 , H01L2924/00014
Abstract: An LED includes a first intermetallic layer, a first metal thin film layer, an LED chip, a substrate, a second metal thin film layer, and a second intermetallic layer. The first metal thin film layer is located on the first intermetallic layer. The LED chip is located on the first metal thin film layer. The second metal thin film layer is located on the substrate. The second intermetallic layer is located on the second metal thin film layer, and the first intermetallic layer is located on the second intermetallic layer. Materials of the first and the second metal thin film layer are selected from a group consisting of Au, Ag, Cu, and Ni. Materials of the intermetallic layers are selected from a group consisting of a Cu—In—Sn intermetallics, an Ni—In—Sn intermetallics, an Ni—Bi intermetallics, an Au—In intermetallics, an Ag—In intermetallics, an Ag—Sn intermetallics, and an Au—Bi intermetallics.
Abstract translation: LED包括第一金属间层，第一金属薄膜层，LED芯片，基板，第二金属薄膜层和第二金属间层。 第一金属薄膜层位于第一金属间层上。 LED芯片位于第一金属薄膜层上。 第二金属薄膜层位于基板上。 第二金属间化合物层位于第二金属薄膜层上，第一金属间化合物层位于第二金属间层上。 第一和第二金属薄膜层的材料选自由Au，Ag，Cu和Ni组成的组。 金属间层的材料选自Cu-In-Sn金属间化合物，Ni-In-Sn金属间化合物，Ni-Bi金属间化合物，Au-In金属间化合物，Ag-In金属间化合物，Ag-Sn 金属间化合物和Au-Bi金属间化合物。
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公开(公告)号：US08440503B1
公开(公告)日：2013-05-14
申请号：US13298056
申请日：2011-11-16
Applicant: Hsiu-Jen Lin , Chih-Wei Lin , Cheng-Ting Chen , Ming-Da Cheng , Chung-Shi Liu
Inventor： Hsiu-Jen Lin , Chih-Wei Lin , Cheng-Ting Chen , Ming-Da Cheng , Chung-Shi Liu
IPC: H01L21/00
CPC classification number: H01L24/75 , H01L24/81 , H01L24/97 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/75283 , H01L2224/7598 , H01L2224/81005 , H01L2224/81136 , H01L2224/81191 , H01L2224/81192 , H01L2224/81193 , H01L2224/8123 , H01L2224/814 , H01L2224/81815 , H01L2224/97 , H01L2924/014 , H01L2924/00012 , H01L2224/81
Abstract: A method includes placing a cover over a lower package component, wherein the cover comprises an opening aligned to the lower package component. An upper package component is placed over the lower package component. The upper package component is aligned to the opening, and a solder region is dispose between the upper package component and the lower package component. The cover and the upper package component are exposed to a radiation to reflow the solder region.
Abstract translation: 一种方法包括将盖子放置在下部封装部件上，其中盖子包括与下部封装部件对准的开口。 上封装组件放置在下封装组件上。 上部封装部件与开口对准，并且焊接区域配置在上部封装部件和下部封装部件之间。 盖和上部封装部件暴露于辐射以回流焊接区域。
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