公开(公告)号：US09431484B2

公开(公告)日：2016-08-30

申请号：US13194362

申请日：2011-07-29

Applicant: Rainald Sander ,  Markus Winkler ,  Michael Asam ,  Matthias Stecher

Inventor： Rainald Sander ,  Markus Winkler ,  Michael Asam ,  Matthias Stecher

IPC: H01L29/76 ,  H01L29/06 ,  H01L29/78 ,  H01L29/40 ,  H01L29/10

CPC classification number: H01L29/7813 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/7805

Abstract: A transistor is disclosed that includes a semiconductor body having a first horizontal surface. A drift region is arranged in the semiconductor body. A plurality of gate electrodes is arranged in trenches of the semiconductor body. The trenches have a longitudinal direction and extending parallel relative to each other. The longitudinal direction of the trenches extends in a first lateral direction of the semiconductor body. The body regions and the source regions are arranged between the trenches. The body regions are arranged between the drift region and the source regions in a vertical direction of the semiconductor body. In the first horizontal surface, the source regions and the body regions are arranged alternately in the first lateral direction. A source electrode is electrically connected to the source regions and the body regions in the first horizontal surface.

Abstract translation: 公开了一种包括具有第一水平表面的半导体本体的晶体管。 漂移区布置在半导体本体中。 多个栅极布置在半导体本体的沟槽中。 沟槽具有纵向并相对于彼此平行延伸。 沟槽的纵向方向在半导体本体的第一横向延伸。 身体区域和源区域布置在沟槽之间。 主体区域在半导体本体的垂直方向上布置在漂移区域和源极区域之间。 在第一水平表面中，源区域和主体区域在第一横向上交替布置。 源电极电连接到第一水平表面中的源极区域和主体区域。

公开(公告)号：US09214424B2

公开(公告)日：2015-12-15

申请号：US13452044

申请日：2012-04-20

Applicant: Matthias Stecher ,  Markus Menath ,  Andreas Zankl ,  Anja Gisslbl

Inventor： Matthias Stecher ,  Markus Menath ,  Andreas Zankl ,  Anja Gisslbl

IPC: H01L21/302 ,  H01L21/461 ,  H01L23/522 ,  H01L21/311 ,  H01L21/322 ,  H01L21/74 ,  H01L21/3115 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L21/76804 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/3115 ,  H01L21/322 ,  H01L21/44 ,  H01L21/743 ,  H01L21/76802 ,  H01L23/5222 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for producing a rounded conductor line of a semiconductor component is disclosed. In that method, a partially completed semiconductor component is provided. The partially completed semiconductor component has a bottom side and a top side spaced distant from the bottom side in a vertical direction. Also provided is an etchant. On the top side, a dielectric layer is arranged. The dielectric layer has at least two different regions that show different etch rates when they are etched with the etchant. Subsequently, a trench is formed in the dielectric layer such that the trench intersects each of the different regions. Then, the trench is widened by etching the trench with the etchant at different etch rates. By filling the widened trench with an electrically conductive material, a conductor line is formed.

Abstract translation: 公开了一种用于制造半导体部件的圆形导线的方法。 在该方法中，提供部分完成的半导体部件。 部分完成的半导体部件具有在垂直方向上与底侧间隔开的底侧和顶侧。 还提供了一种蚀刻剂。 在顶侧设置介电层。 介电层具有至少两个不同的区域，当蚀刻剂用蚀刻剂蚀刻时，其表现出不同的蚀刻速率。 随后，在电介质层中形成沟槽，使得沟槽与不同区域中的每一个相交。 然后，通过用不同蚀刻速率的蚀刻剂蚀刻沟槽来加宽沟槽。 通过用导电材料填充加宽的沟槽，形成导体线。

公开(公告)号：US08569842B2

公开(公告)日：2013-10-29

申请号：US13275151

申请日：2011-10-17

Applicant: Rolf Weis ,  Franz Hirler ,  Matthias Stecher ,  Armin Willmeroth ,  Gerald Deboy ,  Martin Feldtkeller

Inventor： Rolf Weis ,  Franz Hirler ,  Matthias Stecher ,  Armin Willmeroth ,  Gerald Deboy ,  Martin Feldtkeller

IPC: H01L27/06 ,  H01L27/088 ,  H01L27/098 ,  H01L29/161 ,  H01L29/20 ,  H01L29/778 ,  H01L29/788

CPC classification number: H01L27/0207 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0623 ,  H01L27/0629 ,  H01L27/0727 ,  H01L27/088 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/098 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/78 ,  H01L29/7817 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7835 ,  H01L29/7838 ,  H03K17/06

Abstract: A semiconductor device arrangement includes a first semiconductor device having a load path, and a number of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor. Each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors. One of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.

Abstract translation: 半导体器件布置包括具有负载路径的第一半导体器件和多个第二晶体管，每个具有第一和第二负载端子与控制端子之间的负载路径。 第二晶体管的负载路径串联连接并与第一晶体管的负载路径串联连接。 每个第二晶体管的控制端连接到其它第二晶体管的负载端子。 第二晶体管中的一个具有其控制端子连接到第一半导体器件的负载端子之一。

公开(公告)号：US08183125B2

公开(公告)日：2012-05-22

申请号：US13225709

申请日：2011-09-06

Applicant: Matthias Stecher ,  Hans-Joachim Schulze ,  Thomas Neidhart

Inventor： Matthias Stecher ,  Hans-Joachim Schulze ,  Thomas Neidhart

IPC: H01L21/76

CPC classification number: H01L21/823878 ,  H01L21/26506 ,  H01L21/743 ,  H01L21/761 ,  H01L27/0251 ,  H01L27/0921 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and manufacturing method is disclosed. One embodiment provides a common substrate of a first conductivity type and at least two wells of a second conductivity type. A buried high resistivity region and at least an insulating structure is provided insulating the first well from the second well. The insulating structure extends through the buried high resistivity region and includes a conductive plug in Ohmic contact with the first semiconductor region. A method for forming an integrated semiconductor device is also provided.

Abstract translation: 公开了一种半导体器件和制造方法。 一个实施例提供了第一导电类型的公共衬底和第二导电类型的至少两个阱。 提供掩埋的高电阻率区域和至少一个绝缘结构，使第一阱与第二阱绝缘。 绝缘结构延伸穿过掩埋的高电阻率区域并且包括与第一半导体区域欧姆接触的导电插塞。 还提供了一种用于形成集成半导体器件的方法。

公开(公告)号：US20110318904A1

公开(公告)日：2011-12-29

申请号：US13225709

申请日：2011-09-06

Applicant: Matthias Stecher ,  Hans-Joachim Schulze ,  Thomas Neidhart

Inventor： Matthias Stecher ,  Hans-Joachim Schulze ,  Thomas Neidhart

IPC: H01L21/76

CPC classification number: H01L21/823878 ,  H01L21/26506 ,  H01L21/743 ,  H01L21/761 ,  H01L27/0251 ,  H01L27/0921 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and manufacturing method is disclosed. One embodiment provides a common substrate of a first conductivity type and at least two wells of a second conductivity type. A buried high resistivity region and at least an insulating structure is provided insulating the first well from the second well. The insulating structure extends through the buried high resistivity region and includes a conductive plug in Ohmic contact with the first semiconductor region. A method for forming an integrated semiconductor device is also provided.

Abstract translation: 公开了一种半导体器件和制造方法。 一个实施例提供了第一导电类型的公共衬底和第二导电类型的至少两个阱。 提供掩埋的高电阻率区域和至少一个绝缘结构，使第一阱与第二阱绝缘。 绝缘结构延伸穿过掩埋的高电阻率区域并且包括与第一半导体区域欧姆接触的导电插塞。 还提供了一种用于形成集成半导体器件的方法。

公开(公告)号：US08076238B2

公开(公告)日：2011-12-13

申请号：US11859438

申请日：2007-09-21

Applicant: Khalil Hosseini ,  Matthias Stecher

Inventor： Khalil Hosseini ,  Matthias Stecher

IPC: H01L21/44

CPC classification number: H01L24/48 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/81 ,  H01L24/85 ,  H01L2224/0347 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/73257 ,  H01L2224/81801 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/85375 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/00014 ,  H01L2224/05164 ,  H01L2924/00 ,  H01L2924/013 ,  H01L2924/2075 ,  H01L2924/00012 ,  H01L2924/01006

Abstract: An electronic device and method for production is disclosed. One embodiment provides an integrated component having a first layer which is composed of copper or a copper alloy or which contains copper or a copper alloy, and having an electrically conductive second layer, whose material differs from the material of the first layer, and a connection apparatus which is arranged on the first layer and on the second layer.

Abstract translation: 公开了一种用于生产的电子设备和方法。 一个实施例提供了一种集成部件，其具有由铜或铜合金构成的第一层或者包含铜或铜合金的第一层，并且具有导电的第二层，其材料与第一层的材料不同， 设置在第一层和第二层上。

公开(公告)号：US07888782B2

公开(公告)日：2011-02-15

申请号：US11925268

申请日：2007-10-26

Applicant: Peter Nelle ,  Matthias Stecher

Inventor： Peter Nelle ,  Matthias Stecher

IPC: H01L23/495

CPC classification number: H01L23/49513 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/04026 ,  H01L2224/05624 ,  H01L2224/2908 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/83801 ,  H01L2224/83825 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/01028 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00015

Abstract: An apparatus and a method configured to lower thermal stress is disclosed. One embodiment provides a semiconductor chip, a lead frame and a layer structure. The layer structure includes at least a diffusion solder layer and a buffer layer. The layer structure is arranged between the semiconductor chip and the lead frame. The buffer layer includes a material, which is soft in comparison to a material of the diffusion solder layer, and includes a layer thickness such that thermal stresses in the semiconductor chip remain below a predetermined value during temperature fluctuations within a temperature range.

公开(公告)号：US07859082B2

公开(公告)日：2010-12-28

申请号：US11752734

申请日：2007-05-23

Applicant: Matthias Stecher

Inventor： Matthias Stecher

IPC: H01L29/735

CPC classification number: H01L29/735 ,  H01L29/0808 ,  H01L29/0821

Abstract: Emitter and collector regions of the bipolar transistor are formed by doped regions of the same type of conductivity, which are separated by doped semiconductor material of an opposite type of conductivity, the separate doped regions being arranged at a surface of a semiconductor body and being in electric contact with electrically conductive material that is introduced into trenches at the surface of the semiconductor body.

Abstract translation: 双极晶体管的发射极和集电极区域由相同导电类型的掺杂区域形成，这些掺杂区域由相反导电类型的掺杂半导体材料分开，分立的掺杂区域被布置在半导体主体的表面，并且位于 与在半导体本体的表面处被引入到沟槽中的导电材料电接触。

公开(公告)号：US20100213613A1

公开(公告)日：2010-08-26

申请号：US12770017

申请日：2010-04-29

Applicant: Thomas Laska ,  Matthias Stecher ,  Gregory Bellynck ,  Khalil Hosseini ,  Joachim Mahler

Inventor： Thomas Laska ,  Matthias Stecher ,  Gregory Bellynck ,  Khalil Hosseini ,  Joachim Mahler

IPC: H01L23/498 ,  H01L23/49

CPC classification number: H01R12/57 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05556 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/451 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/48472 ,  H01L2224/48611 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48711 ,  H01L2224/48739 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/48992 ,  H01L2224/48997 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/85099 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/8592 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01005 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/12041 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/2076 ,  H01R13/03 ,  H01L2924/01004 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/48811 ,  H01L2224/48744 ,  H01L2924/00012 ,  H01L2924/01006

Abstract: An electrical connection arrangement between a semiconductor circuit arrangement and an external contact device, and to a method for producing the connection arrangement is disclosed. In one embodiment, a metallic layer is deposited onto at least one contact terminal and/or the contacts and the wire, the metallic layer protecting the contact terminal or the electrical connection against ambient influences and ensuring a high reliability.

Abstract translation: 公开了半导体电路装置和外部接触装置之间的电气连接装置，以及用于制造连接装置的方法。 在一个实施例中，金属层沉积在至少一个接触端子和/或触点和导线上，金属层保护接触端子或电连接免受环境影响并确保高可靠性。

公开(公告)号：US07737560B2

公开(公告)日：2010-06-15

申请号：US11436402

申请日：2006-05-18

Applicant: Matthias Stecher ,  Renate Hofmann ,  Joerg Busch

Inventor： Matthias Stecher ,  Renate Hofmann ,  Joerg Busch

IPC: H01L23/48

CPC classification number: H01L24/05 ,  H01L21/76838 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05147 ,  H01L2224/05556 ,  H01L2224/05644 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48644 ,  H01L2224/48699 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/48744

Abstract: A power semiconductor IC device is disclosed. In one embodiment, the device includes a substrate, and a layer structure formed on the substrate. The layer structure includes a metallization layer including copper, wherein the metallization layer is formed as a stack structure including at least two copper layers and a stabilization layer between the two copper layers.

Abstract translation: 公开了功率半导体IC器件。 在一个实施例中，该器件包括衬底和形成在衬底上的层结构。 层结构包括包括铜的金属化层，其中金属化层形成为包括至少两个铜层和两个铜层之间的稳定层的堆叠结构。