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    Chip C4 assembly improvement using magnetic force and adhesive
    11.
    发明授权
    Chip C4 assembly improvement using magnetic force and adhesive 失效
    芯片C4组装改进使用磁力和粘合剂

    公开(公告)号：US6142361A

    公开(公告)日：2000-11-07

    申请号：US458483

    申请日：1999-12-09

    申请人： Francis J. Downes, Jr. ,  Robert M. Japp ,  Mark V. Pierson

    发明人： Francis J. Downes, Jr. ,  Robert M. Japp ,  Mark V. Pierson

    IPC分类号： H01L21/60 ,  H05K3/30 ,  H05K3/34 ,  B23K1/20 ,  B23K31/02

    CPC分类号： H01L24/81 ,  B23K2201/40 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/303 ,  H05K3/3436 ,  Y10T29/4913 ,  Y10T29/53196

    摘要： A method, and associated structure, for adhesively coupling a chip to an organic chip carrier. The chip is attached to a top surface of the organic chip carrier by interfacing a solder bump between a C4 solder structure on the chip and a pad on a top surface of the chip carrier. The melting temperature of the solder bump is less than the melting temperature of the C4 solder structure. A block of ferrous material is placed on a top surface of the chip. A temporary or permanent stiffener of ferrous material is placed on the top surface of the chip carrier. A permanent magnet is coupled to a bottom surface of the chip carrier. Alternatively, an electromagnetic could be utilized instead of the electromagnet. Due to the permanent magnet or the electromagnet, a magnetic force on the stiffener is directed toward the magnet and substantially flattens the first surface of the chip carrier. Similarly, a magnetic force on the block is directed toward the magnet such that the electronic component and the chip carrier are held in alignment. The solder bump is reflowed at a temperature between the melting temperature of the solder bump and the melting temperature of the C4 solder structure. The reflowing reconfigures the solder bump. The magnetic force on the block frictionally clamps the reflowed solder between the C4 solder structure and the pad. The chip and carrier are cooled, resulting in the C4 solder structure being adhesively and conductively coupled to the pad.

    摘要翻译： 一种用于将芯片粘合地耦合到有机芯片载体的方法和相关联的结构。 芯片通过在芯片上的C4焊料结构和芯片载体的顶表面上的焊盘之间接合焊料凸块来附接到有机芯片载体的顶表面。 焊料凸点的熔化温度小于C4焊料结构的熔化温度。 将一块黑色金属材料放置在芯片的上表面上。 铁芯材料的临时或永久性加强件被放置在芯片载体的顶表面上。 永磁体耦合到芯片载体的底表面。 或者，可以使用电磁来代替电磁体。 由于永磁体或电磁体，加强件上的磁力被引向磁体并且基本平坦化芯片载体的第一表面。 类似地，块上的磁力指向磁体，使得电子部件和芯片载体保持对准。 在焊料凸块的熔化温度和C4焊料结构的熔化温度之间的温度下回流焊料凸点。 回流重新配置焊料凸块。 块上的磁力摩擦地夹住C4焊料结构和焊盘之间的回流焊料。 芯片和载体被冷却，导致C4焊料结构被粘性地导电耦合到焊盘。

    METHOD OF FORMING FIBROUS LAMINATE CHIP CARRIER STRUCTURES
    12.
    发明申请
    METHOD OF FORMING FIBROUS LAMINATE CHIP CARRIER STRUCTURES 审中-公开
    形成薄片层状载体结构的方法

    公开(公告)号：US20120012553A1

    公开(公告)日：2012-01-19

    申请号：US12837584

    申请日：2010-07-16

    申请人： Robert M. Japp ,  Kostas I. Papathomas ,  Cheryl Palomaki

    发明人： Robert M. Japp ,  Kostas I. Papathomas ,  Cheryl Palomaki

    IPC分类号： B32B38/10 ,  C23F1/02

    CPC分类号： H05K1/0366 ,  B32B37/02 ,  B32B2309/105 ,  B32B2457/08 ,  H05K3/42 ,  H05K2201/0293 ,  H05K2201/0358 ,  H05K2203/063 ,  Y10T156/1062

    摘要： A method for making a leadless chip carrier (LCC) for use in electronic packages having a core layer stripped of copper cladding, containing drilled clearance holes within, a layer of resin coated copper (RCC) placed on the upper surface of the core layer and a second layer of RCC placed on the lower surface of the core layer. The layers are laminated together with the RCC filling the clearance holes during lamination. A pattern is etched on the RCC and vias are drilled through the filled clearance holes and pre-plated with seed copper layers. The seed copper layers in the vias are then covered by a layer of copper plating to meet the requirements of the core buildup layer, and resin inhibiting conductive anodic filament (CAF) growth within the structure.

    摘要翻译： 一种制造用于电子封装的无引线芯片载体（LCC）的方法，所述无引线芯片载体（LCC）具有剥离铜包层的芯层，其中包含钻孔的间隙孔，放置在芯层的上表面上的树脂涂覆铜层（RCC），以及 第二层RCC放置在芯层的下表面上。 层压在一起，RCC在层压期间填充间隙孔。 在RCC上蚀刻图案，并且通过填充的间隙孔钻出通孔并且预镀有种子铜层。 然后通孔中的种子铜层被镀铜层覆盖以满足堆芯层的要求，并且在结构内树脂抑制导电阳极丝（CAF）生长。

    POWER CORE FOR USE IN CIRCUITIZED SUBSTRATE AND METHOD OF MAKING SAME
    13.
    发明申请
    POWER CORE FOR USE IN CIRCUITIZED SUBSTRATE AND METHOD OF MAKING SAME 有权
    在电路基板中使用的电源芯及其制造方法

    公开(公告)号：US20110284273A1

    公开(公告)日：2011-11-24

    申请号：US12782187

    申请日：2010-05-18

    申请人： Robert M. Japp ,  Kostas Papathomas ,  John S. Kresge ,  Timothy Antesberger

    发明人： Robert M. Japp ,  Kostas Papathomas ,  John S. Kresge ,  Timothy Antesberger

    IPC分类号： H05K1/09 ,  H05K1/00 ,  H01R43/00 ,  H05K1/11

    CPC分类号： H05K3/4641 ,  H05K3/4617 ,  H05K2201/068 ,  Y10T29/49117

    摘要： A power core adapted for use as part of a circuitized substrate, e.g., a PCB or LCC. The core includes a first layer of low expansion dielectric and two added layers of a different low expansion dielectric bonded thereto, with two conductive layers positioned on the two added low expansion dielectric layers. At least one of the conductive layers serves as a power plane for the power core, which in turn is usable within a circuitized substrate, also provided. Methods of making the power core and circuitized substrate are also provided. The use of different low expansion dielectric materials for the power core enables the use of support enhancing fiberglass in one layer while such use is precluded in the other two dielectric layers, thus preventing CAF shorting problems in highly precisely defined thru holes formed within the power core.

    摘要翻译： 适于用作电路化基板（例如PCB或LCC）的一部分的电源核心。 芯包括第一层低膨胀电介质和两个相邻的不同的低膨胀电介质结合的层，其中两个导电层位于两个添加的低膨胀介电层上。 导电层中的至少一个用作功率芯的功率平面，而功率芯也可以在电路化的衬底内使用。 还提供了制造电源芯和电路化基板的方法。 使用不同的低膨胀电介质材料用于电源芯可以在一层中使用支撑增强玻璃纤维，而在其他两个电介质层中排除这种用途，从而防止形成在功率芯内的高度精确定义的通孔中的CAF短路问题 。

    Porous power and ground planes for reduced PCB delamination and better reliability
    16.
    发明授权
    Porous power and ground planes for reduced PCB delamination and better reliability 失效
    多功能电源和接地平面可降低PCB分层和更好的可靠性

    公开(公告)号：US06944946B2

    公开(公告)日：2005-09-20

    申请号：US10430989

    申请日：2003-05-06

    申请人： Robert M. Japp ,  Mark D. Poliks

    发明人： Robert M. Japp ,  Mark D. Poliks

    IPC分类号： H05K1/02 ,  H05K3/38 ,  H05K3/42 ,  H05K3/46 ,  H01K3/10

    CPC分类号： H05K3/38 ,  H05K3/429 ,  H05K3/4641 ,  H05K2201/0116 ,  H05K2201/0281 ,  H05K2201/029 ,  H05K2201/0769 ,  H05K2201/09309 ,  H05K2201/09681 ,  H05K2203/1131 ,  Y10S428/901 ,  Y10T29/49002 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T156/1052 ,  Y10T428/24273 ,  Y10T428/24917

    摘要： Power and ground planes that are used in Printed Circuit Boards (PCBs) and that comprise porous, conductive materials are disclosed. Using porous power and ground plane materials in PCBs allows liquids (e.g., water and/or other solvents) to pass through the power and ground planes, thus decreasing failures in PCBs (or PCBs used as laminate chip carriers) caused by cathodic/anodic filament growth and delamination of insulators. Porous conductive materials suitable for use in PCBs may be formed by using metal-coated organic cloths (such as polyester or liquid crystal polymers) or fabrics (such as those made from carbon/graphite or glass fibers), using metal wire mesh instead of metal sheets, using sintered metal, or making metal sheets porous by forming an array of holes in the metal sheets. Fabrics and mesh may be woven or random. If an array of holes is formed in a metal sheet, such an array may be formed with no additional processing steps than are performed using conventional PCB assembly methods.

    摘要翻译： 公开了在印刷电路板（PCB）中使用并且包含多孔导电材料的电源和接地层。 在PCB中使用多孔电源和接地平面材料可以使液体（例如水和/或其他溶剂）通过电源和接地层，从而减少由阴极/阳极细丝引起的PCB（或PCBs用作层压芯片载体）的故障 绝缘子的生长和分层。 适用于PCB的多孔导电材料可以通过使用金属涂布的有机布（例如聚酯或液晶聚合物）或织物（例如由碳/石墨或玻璃纤维制成的那些）形成，使用金属丝网代替金属 使用烧结金属，或者通过在金属板中形成孔阵列来制造多孔的金属片。 织物和网可以编织或随机。 如果在金属板中形成孔阵列，则可以形成这样的阵列，而不需要使用常规PCB组装方法执行的附加处理步骤。

    Multilayer capacitance structure and circuit board containing the same and method of forming the same
    17.
    发明授权
    Multilayer capacitance structure and circuit board containing the same and method of forming the same 有权
    多层电容结构和电路板含有相同的方法和其形成方法

    公开(公告)号：US06496356B2

    公开(公告)日：2002-12-17

    申请号：US10026873

    申请日：2001-12-21

    申请人： Robert M. Japp ,  John M. Lauffer ,  Konstantinos I. Papathomas

    发明人： Robert M. Japp ,  John M. Lauffer ,  Konstantinos I. Papathomas

    IPC分类号： H01G4228

    CPC分类号： H05K1/162 ,  H05K3/429 ,  H05K3/4611 ,  H05K3/4641 ,  H05K2201/0209 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2203/0759

    摘要： A method of forming a capacitive core structure and of forming a circuitized printed wiring board from the core structure and the resulting structures are provided. The capacitive core structure is formed by providing a central conducting plane of a sheet of conductive material and forming at least one clearance hole in the central conducting plane. First and second external conducting planes are laminated to opposite sides of the ground plane with a film of dielectric material between each of the first and second external planes and the central conducting plane. At least one clearance hole is formed in each of the first and second external planes. A circuitized wiring board structure can be formed by laminating a capacitive core structure between two circuitized structures. The invention also relates to the structures formed by these methods.

    摘要翻译： 提供了一种从芯结构形成电容性芯结构和形成电路化印刷线路板的方法及其结构。 通过提供导电材料片的中心导电平面并在中心导电平面中形成至少一个间隙孔来形成电容芯结构。 第一和第二外部导电平面在第一和第二外部平面之间的介电材料膜和中心导电平面之间层压到接地平面的相对侧。 在第一和第二外部平面的每一个中形成至少一个间隙孔。 可以通过在两个电路化结构之间层叠电容性芯结构来形成电路化布线板结构。 本发明还涉及通过这些方法形成的结构。