公开(公告)号：US10032715B2

公开(公告)日：2018-07-24

申请号：US15601406

申请日：2017-05-22

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Zhuowen Sun

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/522 ,  H01L21/48 ,  H01L21/768 ,  H01L23/14 ,  H01L23/498

Abstract: An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction. At least two metalized vias extend through the semiconductor material layer. A first pair of the at least two metalized vias are spaced apart from each other in a second direction orthogonal to the first direction. A first insulating via in the semiconductor layer extends from the first surface toward the second surface. The insulating via is positioned such that a geometric center of the insulating via is between two planes that are orthogonal to the second direction and that pass through each of the first pair of the at least two metalized vias. A dielectric material at least partially fills the first insulating via or at least partially encloses a void in the insulating via.

公开(公告)号：US09991233B2

公开(公告)日：2018-06-05

申请号：US15393100

申请日：2016-12-28

Applicant: Invensas Corporation

Inventor： Min Tao ,  Hoki Kim ,  Ashok S. Prabhu ,  Zhuowen Sun ,  Wael Zohni ,  Belgacem Haba

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L21/52

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/52 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/5283 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/09 ,  H01L24/46 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/071 ,  H01L25/105 ,  H01L25/112 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/19107

Abstract: Package-on-package (“PoP”) devices with same level wafer-level packaged (“WLP”) components and methods therefor are disclosed. In a PoP device, a first integrated circuit die is surface mount coupled to an upper surface of a package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region. The first conductive lines extend away from the upper surface of the package substrate. A molding layer is formed over the upper surface of the package substrate, around sidewall surfaces of the first integrated circuit die, and around bases and shafts of the conductive lines. WLP microelectronic components are located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines.

公开(公告)号：US20180026018A1

公开(公告)日：2018-01-25

申请号：US15393083

申请日：2016-12-28

Applicant: Invensas Corporation

Inventor： Min Tao ,  Hoki Kim ,  Ashok S. Prabhu ,  Zhuowen Sun ,  Wael Zohni ,  Belgacem Haba

IPC: H01L25/10 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/52 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/5283 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/09 ,  H01L24/46 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/071 ,  H01L25/105 ,  H01L25/112 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/19107

Abstract: Package-on-package (“PoP”) devices with multiple levels and methods therefor are disclosed. In a PoP device, a first integrated circuit die is surface mount coupled to an upper surface of a package substrate. First and second conductive lines are coupled to the upper surface of the package substrate respectively at different heights in a fan-out region. A first molding layer is formed over the upper surface of the package substrate. A first and a second wafer-level packaged microelectronic component are located above an upper surface of the first molding layer respectively surface mount coupled to a first and a second set of upper portions of the first conductive lines. A third and a fourth wafer-level packaged microelectronic component are located above the first and the second wafer-level packaged microelectronic component respectively surface mount coupled to a first and a second set of upper portions of the second conductive lines.

公开(公告)号：US20170186474A1

公开(公告)日：2017-06-29

申请号：US14980709

申请日：2015-12-28

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Zhuowen Sun

IPC: G11C11/4076 ,  G11C11/4093

CPC classification number: G11C11/4076 ,  G11C5/04 ,  G11C7/10 ,  G11C11/4093

Abstract: A dual inline memory module can include a module card having first and second opposed surfaces and a plurality of microelectronic elements each having a surface facing a surface of the module card. The module card can have a plurality of parallel edge contacts, the edge contacts including first and second contacts, the first and second contacts configured to carry command and address information and data signals corresponding to first and second memory channels, respectively, the first memory channel being independent from the second memory channel. Each microelectronic element can have memory storage array function being of type LPDDRx and being configured to sample the command and address information at least twice per clock cycle. The plurality of microelectronic elements can be configured to implement the first and second memory channels. The first and second microelectronic elements can be configured for communication via the first and second contacts, respectively.

公开(公告)号：US20170133081A1

公开(公告)日：2017-05-11

申请号：US15337323

申请日：2016-10-28

Applicant: Invensas Corporation

Inventor： Zhuowen Sun ,  Yong Chen ,  Kyong-Mo Bang

IPC: G11C11/408 ,  H01L25/18 ,  G11C11/409 ,  H01L23/64 ,  G11C5/06 ,  H01L25/065 ,  H01L23/02

CPC classification number: G11C11/4087 ,  G11C5/063 ,  G11C8/18 ,  G11C11/409 ,  H01L23/02 ,  H01L23/3128 ,  H01L23/64 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A microelectronic assembly can include an address bus comprising a plurality of signal conductors each passing sequentially through first, second, third, and fourth connection regions, and first and second microelectronic packages. The first microelectronic package can include first and second microelectronic elements, and the second microelectronic package can include third and fourth microelectronic elements. Each microelectronic element can be electrically coupled to the address bus via the respective connection region. An electrical characteristic between the first and second connection regions can be within a same tolerance of the electrical characteristic between the second and third connection regions.

公开(公告)号：US09640282B1

公开(公告)日：2017-05-02

申请号：US14980189

申请日：2015-12-28

Applicant: Invensas Corporation

Inventor： Yong Chen ,  Zhuowen Sun

IPC: G11C29/00 ,  G11C29/56 ,  G11C29/12

CPC classification number: G11C29/1201 ,  G11C29/48 ,  G11C2029/1206 ,  G11C2029/2602 ,  G11C2229/743 ,  H01L2224/32145 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A method of testing a microelectronic package configured to provide memory access can include energizing terminals of the microelectronic package, the terminals including first terminals configured to carry address information and second terminals configured to carry data signals. The method can also include applying read and write test data signals simultaneously to the first and second sets of second terminals, so as to simultaneously test read and write operation in first and second microelectronic elements of the microelectronic package. The first and second microelectronic elements can be configured to provide access to memory storage array locations in the first and second microelectronic elements. The terminals can also include third terminals configured to receive a test mode input that reconfigures the first and second microelectronic elements to permit simultaneous access to memory storage array locations in the first and second microelectronic elements.

公开(公告)号：US20170117231A1

公开(公告)日：2017-04-27

申请号：US15344990

申请日：2016-11-07

Applicant: Invensas Corporation

Inventor： Abiola Awujoola ,  Zhuowen Sun ,  Wael Zohni ,  Ashok S. Prabhu ,  Willmar Subido

IPC: H01L23/552 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/552 ,  H01L23/49811 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/17051 ,  H01L2224/17181 ,  H01L2224/215 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/4942 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73227 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2924/2075 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05599

Abstract: Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

公开(公告)号：US20160035703A1

公开(公告)日：2016-02-04

申请号：US14448040

申请日：2014-07-31

Applicant: Invensas Corporation

Inventor： Zhuowen Sun ,  Yong Chen ,  Kyong-Mo Bang

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/49816 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/481 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/43 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/00015

Abstract: A microelectronic package can include a substrate comprising a dielectric element having first and second opposite surfaces, and a microelectronic element having a face extending parallel to the first surface. The substrate can also include a plurality of peripheral edges extending between the first and second surfaces defining a generally rectangular or square periphery of the substrate. The substrate can further include a plurality of contacts and terminals, the contacts being at the first surface, the terminals being at at least one of the first or second surfaces. The microelectronic elements can have a plurality of edges bounding the face, and a plurality of element contacts at the face electrically coupled with the terminals through the contacts of the substrate. Each edge of the microelectronic element can be oriented at an oblique angle with respect to the peripheral edges of the substrate.

Abstract translation: 微电子封装可以包括包括具有第一和第二相对表面的电介质元件的基板和具有平行于第一表面延伸的面的微电子元件。 衬底还可以包括在第一和第二表面之间延伸的多个外围边缘，其限定基底的大致矩形或正方形的周边。 所述基板还可包括多个触点和端子，所述触点位于所述第一表面处，所述端子处于所述第一或第二表面中的至少一个。 微电子元件可以具有限定该面的多个边缘，并且在该表面处的多个元件触点通过基板的触点与端子电耦合。 微电子元件的每个边缘可以相对于衬底的周边边缘倾斜地定向。

公开(公告)号：US20150327367A1

公开(公告)日：2015-11-12

申请号：US14275741

申请日：2014-05-12

Applicant: Invensas Corporation

Inventor： Hong SHEN ,  Zhuowen Sun ,  Charles G. Woychik ,  Arkalgud Sitaram

IPC: H05K1/11 ,  H05K1/14 ,  H05K1/18 ,  H05K1/02 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/49833 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/538 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/1615 ,  H01L2924/16153 ,  H01L2924/16251 ,  H01L2924/181 ,  H05K1/0271 ,  H05K1/111 ,  H05K1/141 ,  H05K1/181 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A combined interposer (120) includes multiple constituent interposers (120.i), each with its own substrate (120.iS) and with a circuit layer (e.g. redistribution layer) on top and/or bottom of the substrate. The top circuit layers can be part of a common circuit layer (120R.T) which can interconnect different interposers. Likewise, the bottom circuit layers can be part of a common circuit layer (120R.B). The constituent interposer substrates (120.iS) are initially part of a common wafer, and the common top circuit layer is fabricated before separation of the constituent interposer substrates from the wafer. Use of separated substrates reduces stress compared to use of a single large substrate. Other features are also provided.

Abstract translation: 组合插入器（120）包括多个成分插入件（120.i），每个具有其自己的衬底（120.iS）并且在衬底的顶部和/或底部上具有电路层（例如再分配层）。 顶层电路层可以是可以互连不同插入件的公共电路层（120R.T）的一部分。 类似地，底部电路层可​​以是公共电路层（120R.B）的一部分。 成分插入器基板（120.iS）最初是公共晶片的一部分，并且在将成分插入器基板与晶片分离之前制造公共顶层电路层。 与使用单个大型基材相比，分离的基材的使用降低了应力。 还提供其他功能。

公开(公告)号：US09070423B2

公开(公告)日：2015-06-30

申请号：US14075020

申请日：2013-11-08

Applicant: Invensas Corporation

Inventor： Richard Dewitt Crisp ,  Yong Chen ,  Belgacem Haba ,  Wael Zohni ,  Zhuowen Sun

IPC: G11C5/00 ,  G11C5/02 ,  G11C8/00 ,  G11C8/18 ,  H01L23/00 ,  H01L25/065 ,  G11C5/04 ,  G11C5/06 ,  G11C8/12 ,  H01L23/538

CPC classification number: G11C5/025 ,  G11C5/04 ,  G11C5/063 ,  G11C8/12 ,  G11C11/408 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/00 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A microelectronic package can include a support element having first and second surfaces and substrate contacts at the first or second surface, zeroth and first stacked microelectronic elements electrically coupled with the substrate contacts, and terminals at the second surface electrically coupled with the microelectronic elements. The second surface can have a southwest region encompassing entire lengths of south and west edges of the second surface and extending in orthogonal directions from the south and west edges one-third of each distance toward north and east edges of the second surface, respectively. The terminals can include first terminals at a southwest region of the second surface, the first terminals configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of the memory storage arrays of at least one of the zeroth or first microelectronic elements.

Abstract translation: 微电子封装可以包括具有第一和第二表面的第一表面和第二表面的支撑元件以及与第一表面或第二表面的第一和第二堆叠的微电子元件，以及与第二表面电连接的第二表面的端子与微电子元件电耦合。 第二表面可以具有包括第二表面的南部和西部边缘的整个长度的西南区域，并且在从每个距离的南部和西部边缘的正交方向上分别向第二表面的北部和东部边缘延伸。 终端可以包括在第二表面的西南区域的第一终端，第一终端被配置为携带可用于微电子封装内的电路的地址信息，以从存储器存储阵列的所有可寻址的存储器位置中确定可寻址存储器位置 第一或第一微电子元件中的至少一个。