公开(公告)号：US07157363B2

公开(公告)日：2007-01-02

申请号：US10949386

申请日：2004-09-27

申请人： Takanao Suzuki ,  Masatoshi Inaba ,  Tadanori Ominato ,  Masahiro Kaizu ,  Akihito Kurosaka ,  Masatoshi Inaba ,  Nobuyuki Sadakata ,  Mutsumi Masumoto ,  Kenji Masumoto

发明人： Takanao Suzuki ,  Masatoshi Inaba ,  Tadanori Ominato ,  Masahiro Kaizu ,  Akihito Kurosaka ,  Masatoshi Inaba ,  Nobuyuki Sadakata ,  Mutsumi Masumoto ,  Kenji Masumoto

IPC分类号： H01L21/44

CPC分类号： H01L24/10 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0231 ,  H01L2224/02351 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/13 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00014

摘要： An insulating layer (3) having an opening portion (3a) at a position conformable to an electrode pad (2) is formed. Next, a resin projection portion (4) is formed on the insulating layer (3). Thereafter, a resist film is formed which has opening portions made in regions conformable to the opening portion (3a), the resin projection portion (4) and the region sandwiched therebetween. A Cu plating layer (6) is formed by electrolytic copper plating, using the resist film as a mask.

摘要翻译： 形成在与电极焊盘（2）相适应的位置处具有开口部（3a）的绝缘层（3）。 接着，在绝缘层（3）上形成树脂突起部（4）。 此后，形成抗蚀剂膜，该抗蚀剂膜具有在与开口部分（31a）相适应的区域中形成的开口部分，树脂突出部分（4）和夹在其间的区域。 通过使用抗蚀剂膜作为掩模，通过电解铜电镀形成Cu镀层（6）。

公开(公告)号：US06734532B2

公开(公告)日：2004-05-11

申请号：US10006576

申请日：2001-12-06

申请人： Sreenivasan K. Koduri ,  Kenji Masumoto ,  Mutsumi Masumoto

发明人： Sreenivasan K. Koduri ,  Kenji Masumoto ,  Mutsumi Masumoto

IPC分类号： H01L2358

CPC分类号： H01L23/562 ,  H01L23/3157 ,  H01L23/552 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01055 ,  H01L2924/01087 ,  H01L2924/04941

摘要： A semiconductor device comprising a semiconductor chip having an active and a passive surface; the active surface includes an integrated circuit and input/output pads suitable for metallurgical contacts. Further, the device has a protective plastic film (polyimide, epoxy resin, or silicone) of controlled and uniform thickness (20 to 60 &mgr;m) selectively attached to the passive surface. The film is suitable to absorb light of visible and ultraviolet wavelengths, to remain insensitive to moisture absorption, and to exert thermomechanical stress on the chip such that this stress at least partially neutralizes the stress exerted by an outside part after chip assembly.

摘要翻译： 一种半导体器件，包括具有有源和无源表面的半导体芯片; 主动表面包括集成电路和适用于冶金接触的输入/输出焊盘。 此外，该装置具有选择性地连接到被动表面的受控均匀厚度（20至60μm）的保护性塑料膜（聚酰亚胺，环氧树脂或硅树脂）。 该膜适于吸收可见光和紫外线波长的光，对吸湿不敏感，并在芯片上施加热机械应力，使得该应力至少部分地中和芯片组装后由外部部分施加的应力。

公开(公告)号：US06716674B2

公开(公告)日：2004-04-06

申请号：US09952038

申请日：2001-09-11

申请人： Kiyoshi Yajima ,  Mutsumi Masumoto ,  Chihiro Hatano ,  Kimitaka Nishio ,  Noriyuki Kirikae

发明人： Kiyoshi Yajima ,  Mutsumi Masumoto ,  Chihiro Hatano ,  Kimitaka Nishio ,  Noriyuki Kirikae

IPC分类号： H01L2144

CPC分类号： H01L21/6836 ,  H01L21/78 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2221/68327 ,  H01L2224/274 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/45144 ,  H01L2224/83191 ,  H01L2224/83805 ,  H01L2224/83855 ,  H01L2224/85207 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01025 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/00 ,  H01L2924/01014 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929

摘要： A semiconductor package production method containing a step in which a bond layer made of a single-layer film thermoset bond is provided on the back of a wafer on which many semiconductor devices are formed, a dicing tape is pasted onto its bond layer side, and the bond layer and the wafer are diced simultaneously in order to obtain semiconductor devices with the bond layer, and a step in which the semiconductor devices with the bond layer are detached from the dicing tape and die-attached to interposing substrates serving as bodies to which they are bonded; wherein, the aforementioned film thermoset bond contains an epoxy resin, an epoxy resin hardener, and a phenoxy resin as well as 50-80 wt % of spherical silica, and the bond layer is 100 &mgr;m or thicker. A semiconductor device made by this method and a wafer for use with this method.

摘要翻译： 一种半导体封装件的制造方法，其特征在于，在形成有许多半导体器件的晶片的背面设置有由单层膜热固接合而形成的接合层的步骤，将切割带贴合在其接合层侧， 同时切割接合层和晶片以获得具有接合层的半导体器件，并且其中具有接合层的半导体器件与切割带分离并且模具附接到作为其的主体的插入基板的步骤 他们是保税的 其中，上述膜热固性粘合剂含有环氧树脂，环氧树脂固化剂和苯氧基树脂以及50〜80重量％的球形二氧化硅，并且接合层为100μm以上。 通过该方法制造的半导体器件和用于该方法的晶片。

公开(公告)号：US08381967B1

公开(公告)日：2013-02-26

申请号：US13343941

申请日：2012-01-05

申请人： Mutsumi Masumoto ,  Jesus Bajo Bautista, Jr. ,  Raymond Maldan Partosa ,  James Raymond Baello

发明人： Mutsumi Masumoto ,  Jesus Bajo Bautista, Jr. ,  Raymond Maldan Partosa ,  James Raymond Baello

IPC分类号： B23K31/02

CPC分类号： B23K1/0016 ,  B23K3/0623 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2924/014 ,  H01L2924/00012

摘要： Methods of connecting solder bumps located on dies to leads located on substrates are disclosed herein. One embodiment includes applying a first compression force between the solder bump and the lead; relieving the first compression force between the solder bump and the lead; and applying a second compression force between the solder bump and the lead.

摘要翻译： 本文公开了将位于管芯上的焊料凸块连接到位于衬底上的引线的方法。 一个实施例包括在焊料凸块和引线之间施加第一压缩力; 消除焊料凸块与引线之间的第一压缩力; 以及在所述焊料凸块和所述引线之间施加第二压缩力。

公开(公告)号：US07947602B2

公开(公告)日：2011-05-24

申请号：US12033653

申请日：2008-02-19

申请人： Chizuko Ito ,  Mutsumi Masumoto

发明人： Chizuko Ito ,  Mutsumi Masumoto

IPC分类号： H01L21/44

CPC分类号： H05K1/111 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/49838 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/1148 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/16237 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K3/3452 ,  H05K3/3484 ,  H05K2201/09727 ,  H05K2201/0989 ,  H05K2201/10674 ,  H05K2203/0278 ,  H05K2203/043 ,  Y02P70/611 ,  Y10T29/49151 ,  H01L2924/00012 ,  H01L2924/00

摘要： The objective of the present invention is to offer a method for forming a conductive pattern on a substrate and solder protrusions on the conductive pattern. The pitch of the conductive pattern corresponds to the pitch of electrodes on a semiconductor chip.

摘要翻译： 本发明的目的是提供一种在衬底上形成导电图案并在导电图案上形成焊料突起的方法。 导电图案的间距对应于半导体芯片上的电极间距。

公开(公告)号：US07851264B2

公开(公告)日：2010-12-14

申请号：US12400499

申请日：2009-03-09

申请人： Mutsumi Masumoto

发明人： Mutsumi Masumoto

IPC分类号： H01L21/00

CPC分类号： H01L21/561 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

摘要： The objective of the invention is to provide a semiconductor device manufacturing method with which the generation of burrs can be suppressed while increasing the singulation speed of the package. In a manufacturing method of a QFN package of the present invention, a molding prepared by sealing a lead frame with plural semiconductor chips carried on it en bloc with a resin; the operation comprises the following processing steps: a first singulation processing step S101 in which the molding is half-cut along the cutting plane; a de-flashing processing step S102 in which the burrs on the cut portion of the half-cut molding are removed; and a second singulation processing step S103 in which the de-flashed molding is completely cut along the cutting plane.

摘要翻译： 本发明的目的是提供一种半导体器件制造方法，通过该方法可以抑制毛刺的产生，同时增加封装的单片化速度。 在本发明的QFN封装的制造方法中，通过将具有多个半导体芯片的引线框与树脂一体地密封而成的模制品; 该操作包括以下处理步骤：第一分割处理步骤S101，其中模制件沿切割平面半切; 去除半切成型体的切割部分的毛刺的去闪烁处理步骤S102; 以及第二切割处理步骤S103，其中去闪光成型件沿着切割平面被完全切割。

公开(公告)号：US06929971B2

公开(公告)日：2005-08-16

申请号：US10302254

申请日：2002-11-22

申请人： Kensho Murata ,  Mutsumi Masumoto ,  Kenji Masumoto

发明人： Kensho Murata ,  Mutsumi Masumoto ,  Kenji Masumoto

IPC分类号： H01L21/56 ,  H01L21/60 ,  H01L23/485 ,  H05K3/34 ,  H01L21/00

CPC分类号： H01L21/56 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05023 ,  H01L2224/05024 ,  H01L2224/0508 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/11334 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H05K3/3436 ,  H05K2201/0379 ,  H05K2201/10234 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2224/13099

摘要： Improve the productivity and cost for the manufacturing of a semiconductor device referred to as a wafer level CSP. The manufacturing method for a semiconductor device related to this invention contains each of the processes that form a wiring (18) for the purpose of electrically connecting each electrode pad (10a) and external connecting terminals on top of a wafer (10) on which semiconductor elements are formed, connect conductive balls that are preformed by a separate process on top of this, and next, cover the above-mentioned wafer with a resin (32) such that the upper portion of the conductive supporting posts (30) are exposed. In a later process, solder balls (34) are arranged as external connecting terminals on the upper portion of the conductive supporting posts, and in the final process, semiconductor elements are formed by dicing the above-mentioned wafer along the boundary lines of the above-mentioned semiconductor elements.

摘要翻译： 提高制造称为晶片级CSP的半导体器件的生产率和成本。 与本发明相关的半导体器件的制造方法包含形成布线（18）的每个工艺，其用于将每个电极焊盘（10a）和外部连接端子电连接到晶片（10）的顶部上， 形成半导体元件，连接通过其上的单独工艺预成型的导电球，接下来，用树脂（32）覆盖上述晶片，使得导电支撑柱（30）的上部暴露 。 在后面的处理中，焊球（34）被布置为导电支柱上部的外部连接端子，最后，通过沿着上述边界线对上述晶片进行切割而形成半导体元件 所述半导体元件。

公开(公告)号：US06835595B1

公开(公告)日：2004-12-28

申请号：US09744976

申请日：2001-06-04

申请人： Takanao Suzuki ,  Masatoshi Inaba ,  Tadanori Ominato ,  Masahiro Kaizu ,  Akihito Kurosaka ,  Masatoshi Inaba ,  Nobuyuki Sadakata ,  Mutsumi Masumoto ,  Kenji Masumoto

发明人： Takanao Suzuki ,  Masatoshi Inaba ,  Tadanori Ominato ,  Masahiro Kaizu ,  Akihito Kurosaka ,  Masatoshi Inaba ,  Nobuyuki Sadakata ,  Mutsumi Masumoto ,  Kenji Masumoto

IPC分类号： H01L2144

CPC分类号： H01L24/10 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0231 ,  H01L2224/02351 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/13 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00014

摘要： An insulating layer (3) having an opening portion (3a) at a position conformable to an electrode pad (2) is formed. Next, a resin projection portion (4) is formed on the insulating layer (3). Thereafter, a resist film is formed which has opening portions made in regions conformable to the opening portion (3a), the resin projection portion (4) and the region sandwiched therebetween. A Cu plating layer (6) is formed by electrolytic copper plating, using the resist film as a mask.

摘要翻译： 形成在与电极焊盘（2）一致的位置具有开口部（3a）的绝缘层（3）。 接着，在绝缘层（3）上形成树脂突起部（4）。 此后，形成抗蚀剂膜，其具有在与开口部分（3a），树脂突出部分（4）和夹在其间的区域相适应的区域中形成的开口部分。 通过使用抗蚀剂膜作为掩模，通过电解铜电镀形成Cu镀层（6）。

公开(公告)号：US20100314745A1

公开(公告)日：2010-12-16

申请号：US12482855

申请日：2009-06-11

申请人： Kenji Masumoto ,  Mutsumi Masumoto

发明人： Kenji Masumoto ,  Mutsumi Masumoto

IPC分类号： H01L23/498 ,  H01L21/60

CPC分类号： H01L23/49811 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/13016 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/16057 ,  H01L2224/81136 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor device assembly can include a semiconductor chip, a receiving substrate, and a spacer structure interposed between the semiconductor chip and the receiving substrate. The spacer provides an unoccupied space between a pillar and a bond finger for excess conductive material, which can otherwise flow from between the pillar and bond finger and result in a conductive short. The spacer can also provide an offset between the pillar and bond finger.

摘要翻译： 半导体器件组件可以包括半导体芯片，接收衬底和插入在半导体芯片和接收衬底之间的间隔结构。 间隔件在柱和粘结指之间提供了一个空余的空余物，用于过剩的导电材料，否则可能会从柱和键指之间流出，导致导电短路。 间隔件还可以提供柱和粘合指之间的偏移。

公开(公告)号：US20100032802A1

公开(公告)日：2010-02-11

申请号：US12539122

申请日：2009-08-11

申请人： Shinichi Togawa ,  Mutsumi Masumoto

发明人： Shinichi Togawa ,  Mutsumi Masumoto

IPC分类号： H01L23/498 ,  H01L29/92 ,  H01L21/768 ,  H01L21/50

CPC分类号： H01L23/50 ,  H01L23/49589 ,  H01L23/642 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0502 ,  H01L2224/05099 ,  H01L2224/0555 ,  H01L2224/05554 ,  H01L2224/0556 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/48799 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85205 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

摘要： The objective of this invention is to provide an assembling method for electronic members characterized by the fact that electronic members can be joined reliably and easily without using solder paste. The semiconductor device of the present invention has the following parts: silicon substrate 100 with circuit elements formed on it, plural protrusion-shaped metal electrodes 110A, 110B formed on silicon substrate 100, and capacitor 140 having Au-plated electrodes 142, 144. The electrodes 142, 144 of capacitor 140 are metallurgically joined to protrusion-shaped metal electrodes 110A, 110B by means of ultrasonic thermo-compression bonding.

摘要翻译： 本发明的目的是提供一种用于电子部件的组装方法，其特征在于，电子部件可以可靠且容易地接合而不使用焊膏。 本发明的半导体装置具有：形成有电路元件的硅基板100，形成在硅基板100上的多个突起状金属电极110A，110B，以及具有镀金电极142,144的电容器140。 电容器140的电极142,144通过超声波热压接合冶金地连接到突起状金属电极110A，110B。