公开(公告)号：US20150235991A1

公开(公告)日：2015-08-20

申请号：US14254494

申请日：2014-04-16

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Ratibor Radojcic ,  Dong Wook Kim

IPC: H01L25/065 ,  H05K1/11 ,  H01L23/00 ,  H05K1/09 ,  H01L23/31 ,  H01L23/522

CPC classification number: H01L25/0655 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/145 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/17 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/1712 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/18161 ,  H05K1/09 ,  H05K1/115 ,  H05K2201/09845 ,  H05K2201/10242 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2924/00

Abstract: A bottom package substrate is provided that includes a plurality of metal posts that electrically couple through a die-side redistribution layer to a plurality of die interconnects. The metal posts and the die interconnects are plated onto a seed layer on the bottom package substrate.

Abstract translation: 提供了底部封装基板，其包括多个金属柱，其通过裸片侧再分配层电耦合到多个管芯互连。 金属柱和管芯互连电镀在底部封装衬底上的晶种层上。

公开(公告)号：US09633977B1

公开(公告)日：2017-04-25

申请号：US15040902

申请日：2016-02-10

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Shiqun Gu ,  Urmi Ray ,  Ratibor Radojcic

IPC: H01L25/065 ,  H05K1/14 ,  H01L23/538 ,  H01L23/498 ,  H01L25/16 ,  H01L25/00 ,  H01L21/48

CPC classification number: H01L25/0655 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/49894 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5387 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/10 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/92144 ,  H01L2924/19105 ,  H05K1/14 ,  H05K1/148 ,  H05K1/185 ,  H05K3/4691 ,  H05K2201/09127 ,  H05K2201/10674 ,  H05K2203/0191

Abstract: Some features pertain to an integrated device that include a first integrated circuit (IC) package comprising a first laminated substrate, a flexible connector coupled to the first laminated substrate, and a second integrated circuit (IC) package comprising a second laminated substrate. The second laminated substrate is coupled to the flexible connector. The flexible connector includes a dielectric layer and an interconnect. The dielectric layer and the interconnect substantially extend into the first laminated substrate and the second laminated substrate. In some implementations, the dielectric layer and the interconnect of the flexible connector, contiguously extend into the first laminated substrate and the second laminated substrate. In some implementations, the dielectric layer extends into a substantial portion of the first laminated substrate. In some implementations, the dielectric layer includes polyimide (PI) layer.

公开(公告)号：US20170063079A1

公开(公告)日：2017-03-02

申请号：US14838034

申请日：2015-08-27

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Eugene Robert Worley ,  Ratibor Radojcic ,  Urmi Ray

IPC: H02H9/04

CPC classification number: H02H9/046 ,  H01L23/48 ,  H01L23/60 ,  H01L23/62 ,  H01L27/0255 ,  H01L27/0292 ,  H01L27/0296 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/181 ,  H02H9/044 ,  H01L2924/00012

Abstract: An integrated circuit (IC) package includes a die, a package substrate coupled to the die, and a first electrostatic discharge (ESD) protection component coupled to the package substrate, where the first electrostatic discharge (ESD) protection component is configured to provide package level electrostatic discharge (ESD) protection. In some implementations, the first electrostatic discharge (ESD) protection component is embedded in the package substrate. In some implementations, the die includes an internal electrostatic discharge (ESD) protection component configured to provide die level electrostatic discharge (ESD) protection. In some implementations, the internal electrostatic discharge (ESD) protection component and the first electrostatic discharge (ESD) protection component are configured to provide cumulative electrostatic discharge (ESD) protection for the die.

Abstract translation: 集成电路（IC）封装包括管芯，耦合到管芯的封装衬底以及耦合到封装衬底的第一静电放电（ESD）保护元件，其中第一静电放电（ESD）保护元件被配置为提供封装 级静电放电（ESD）保护。 在一些实施方案中，第一静电放电（ESD）保护组件嵌入在封装衬底中。 在一些实施方案中，管芯包括配置成提供管芯级静电放电（ESD）保护的内部静电放电（ESD）保护部件。 在一些实施方案中，内部静电放电（ESD）保护部件和第一静电放电（ESD）保护部件被配置为为管芯提供累积静电放电（ESD）保护。

公开(公告)号：US09418877B2

公开(公告)日：2016-08-16

申请号：US14324136

申请日：2014-07-04

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Ratibor Radojcic ,  Dong Wook Kim ,  Jae Sik Lee

IPC: H01L21/56 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L23/48 ,  H01L23/498 ,  H01L21/768 ,  H01L23/31 ,  H01L23/14 ,  H01L25/10 ,  H01L23/15

CPC classification number: H01L21/568 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/145 ,  H01L23/15 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/171 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81895 ,  H01L2224/81896 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/1434 ,  H01L2924/1517 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/18161 ,  H05K3/4688 ,  H01L2924/014

Abstract: Some novel features pertain to an integrated device (e.g., integrated package) that includes a base portion for the integrated device, a first die (e.g., first wafer level die), and a second die (e.g., second wafer level die). The base portion includes a first inorganic dielectric layer, a first set of interconnects located in the first inorganic dielectric layer, a second dielectric layer different from the first inorganic dielectric layer, and a set of redistribution metal layers in the second dielectric layer. The first die is coupled to a first surface of the base portion. The second die is coupled to the first surface of the base portion, the second die is electrically coupled to the first die through the first set of interconnects.

Abstract translation: 一些新颖的特征涉及集成器件（例如，集成封装），其包括用于集成器件的基底部分，第一管芯（例如，第一晶片级管芯）和第二管芯（例如，第二晶片级管芯）。 基部包括第一无机电介质层，位于第一无机电介质层中的第一组互连，不同于第一无机介电层的第二电介质层和第二介电层中的一组再分布金属层。 第一管芯耦合到基部的第一表面。 第二管芯耦合到基部的第一表面，第二管芯通过第一组互连件电耦合到第一管芯。

公开(公告)号：US09285418B2

公开(公告)日：2016-03-15

申请号：US13793880

申请日：2013-03-11

Applicant: QUALCOMM Incorporated

Inventor： Tapan J Chakraborty ,  Rajamani Sethuram ,  Ratibor Radojcic

IPC: G01R31/26 ,  H01L21/66 ,  G01R31/28

CPC classification number: G01R31/2874 ,  G01R31/2856 ,  G01R31/2875

Abstract: Apparatus and methods are described herein for emulating the hot spot distribution of a functional test by applying vectors for structural test to an integrated circuit (IC). The affects of the hot spots can then be tested and characterized. The vectors may be generated on the IC, or may be fed to the IC via an external source.

Abstract translation: 本文描述了用于通过将结构测试的向量应用于集成电路（IC）来模拟功能测试的热点分布的装置和方法。 然后可以测试和表征热点的影响。 矢量可以在IC上产生，或者可以经由外部源馈送到IC。

公开(公告)号：US20150325509A1

公开(公告)日：2015-11-12

申请号：US14273882

申请日：2014-05-09

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Dong Wook Kim ,  Jae Sik Lee ,  Shiqun Gu ,  Ratibor Radojcic

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H05K1/11 ,  H01L23/522 ,  H01L23/528 ,  H01L21/311 ,  H05K1/09 ,  H01L21/78 ,  H01L25/065

CPC classification number: H01L23/49827 ,  H01L21/31127 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16235 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81466 ,  H01L2224/81484 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/20648 ,  H01L2924/3511 ,  H05K1/09 ,  H05K1/115 ,  H05K2201/09563 ,  H01L2924/014 ,  H01L2224/81

Abstract: A substrate block is provided that has an increased width. The substrate block comprises two substrate bars, and the substrate bars each comprise a substrate and a plurality of filled vias through the substrate. The substrate block may be used to manufacture package substrates, and these package substrate may be incorporated into a PoP structure. The package substrate includes a carrier having a plurality of vertical interconnections and a bar coupled to the vertical interconnections.

Abstract translation: 提供具有增加的宽度的衬底块。 衬底块包括两个衬底条，并且衬底条各自包括衬底和穿过衬底的多个填充的通孔。 衬底块可以用于制造封装衬底，并且这些封装衬底可以并入PoP结构中。 封装衬底包括具有多个垂直互连的载体和耦合到垂直互连的条。

公开(公告)号：US20140306349A1

公开(公告)日：2014-10-16

申请号：US13861086

申请日：2013-04-11

Applicant: QUALCOMM INCORPORATED

Inventor： Shiqun Gu ,  Urmi Ray ,  Roawen Chen ,  Brian Matthew Henderson ,  Ratibor Radojcic ,  Matthew Nowak ,  Nicholas Yu

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49811 ,  H01L21/486 ,  H01L23/147 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: Some implementations provide an interposer that includes a substrate, a via in the substrate, and an oxidation layer. The via includes a metal material. The oxidation layer is between the via and the substrate. In some implementations, the substrate is a silicon substrate. In some implementations, the oxidation layer is a thermal oxide formed by exposing the substrate to heat. In some implementations, the oxidation layer is configured to provide electrical insulation between the via and the substrate. In some implementations, the interposer also includes an insulation layer. In some implementations, the insulation layer is a polymer layer. In some implementations, the interposer also includes at least one interconnect on the surface of the interposer. The at least one interconnect is positioned on the surface of the interposer such that the oxidation layer is between the interconnect and the substrate.

Abstract translation: 一些实施方案提供了一种插入器，其包括衬底，衬底中的通孔和氧化层。 通孔包括金属材料。 氧化层位于通孔和衬底之间。 在一些实施方式中，衬底是硅衬底。 在一些实施方案中，氧化层是通过将基底暴露于热而形成的热氧化物。 在一些实施方案中，氧化层被配置为在通孔和基底之间提供电绝缘。 在一些实施方案中，插入件还包括绝缘层。 在一些实施方案中，绝缘层是聚合物层。 在一些实现中，插入器还包括在插入器的表面上的至少一个互连。 所述至少一个互连件位于所述插入件的表面上，使得所述氧化层位于所述互连件和所述基板之间。

公开(公告)号：US08691707B2

公开(公告)日：2014-04-08

申请号：US13956703

申请日：2013-08-01

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Ratibor Radojcic ,  Yiming Li

IPC: H01L21/31

CPC classification number: H01L23/62 ,  H01L23/29 ,  H01L23/60 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A voltage-switchable dielectric layer may be employed on a die for electrostatic discharge (ESD) protection. The voltage-switchable dielectric layer functions as a dielectric layer between terminals of the die during normal operation of the die. When ESD events occur at the terminals of the die, a high voltage between the terminals switches the voltage-switchable dielectric layer into a conducting layer to allow current to discharge to a ground terminal of the die without the current passing through circuitry of the die. Thus, damage to the circuitry of the die is reduced or prevented during ESD events on dies with the voltage-switchable dielectric layer. The voltage-switchable dielectric layer may be deposited on the back side of a die for protection during stacking with a second die to form a stacked IC. A method includes depositing a voltage-switchable dielectric layer on a first die between a first terminal and a second terminal.

Abstract translation: 可以在用于静电放电（ESD）保护的管芯上使用电压可切换电介质层。 电压切换介电层在芯片的正常操作期间用作模具的端子之间的介电层。 当在芯片的端子处发生ESD事件时，端子之间的高电压将可切换电压的电介质层切换成导电层，以允许电流放电到裸片的接地端，而不会流过电流通过电路的电路。 因此，在具有可电压切换介电层的管芯上的ESD事件期间，对管芯电路的损坏被减小或防止。 电压可切换电介质层可以沉积在管芯的背面上，用于在与第二管芯堆叠期间进行保护以形成堆叠的IC。 一种方法包括在第一端子和第二端子之间的第一管芯上沉积可电压切换介电层。