公开(公告)号：US08963312B2

公开(公告)日：2015-02-24

申请号：US14339341

申请日：2014-07-23

Applicant: Xintec Inc.

Inventor： Yen-Shih Ho ,  Tsang-Yu Liu ,  Shu-Ming Chang ,  Yu-Lung Huang ,  Chao-Yen Lin ,  Wei-Luen Suen ,  Chien-Hui Chen

IPC: H01L23/02 ,  H01L23/48 ,  H01L21/44 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/49 ,  G06K9/00053 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/02381 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/06135 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/43 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48599 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48669 ,  H01L2224/48687 ,  H01L2224/4869 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/146 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A stacked chip package including a device substrate having an upper surface, a lower surface and a sidewall is provided. The device substrate includes a sensing region or device region, a signal pad region and a shallow recess structure extending from the upper surface toward the lower surface along the sidewall. A redistribution layer is electrically connected to the signal pad region and extends into the shallow recess structure. A wire has a first end disposed in the shallow recess structure and electrically connected to the redistribution layer, and a second end electrically connected to a first substrate and/or a second substrate disposed under the lower surface. A method for forming the stacked chip package is also provided.

Abstract translation: 提供了包括具有上表面，下表面和侧壁的器件衬底的堆叠芯片封装。 器件衬底包括感测区域或器件区域，信号焊盘区域和沿着侧壁从上表面向下表面延伸的浅凹陷结构。 再分配层电连接到信号焊盘区域并延伸到浅凹陷结构中。 电线具有设置在浅凹陷结构中并电连接到再分布层的第一端，以及电连接到设置在下表面下方的第一基板和/或第二基板的第二端。 还提供了一种用于形成堆叠芯片封装的方法。

公开(公告)号：US08928098B2

公开(公告)日：2015-01-06

申请号：US13714218

申请日：2012-12-13

Applicant: Xintec Inc.

Inventor： Hung-Jen Lee ,  Shu-Ming Chang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/007 ,  B81C1/0023 ,  B81C1/00301

Abstract: A semiconductor package includes: a chip having a first portion and a second portion disposed on the first portion, wherein the second portion has at least a through hole therein for exposing a portion of the first portion, and the first portion and/or the second portion has a MEMS; and an etch stop layer formed between the first portion and the second portion and partially exposed through the through hole of the second portion. The invention allows an electronic element to be received in the through hole so as for the semiconductor package to have integrated functions of the MEMS and the electronic element. Therefore, the need to dispose the electronic element on a circuit board as in the prior art can be eliminated, thereby saving space on the circuit board.

Abstract translation: 半导体封装包括：具有第一部分和设置在第一部分上的第二部分的芯片，其中第二部分至少在其中具有用于暴露第一部分的一部分的通孔，以及第一部分和/或第二部分 部分具有MEMS; 以及形成在所述第一部分和所述第二部分之间并且部分地暴露于所述第二部分的通孔的蚀刻停止层。 本发明允许电子元件被容纳在通孔中，以便半导体封装具有MEMS和电子元件的集成功能。 因此，可以消除如现有技术那样将电子元件配置在电路板上，从而节省了电路板上的空间。

公开(公告)号：US10049252B2

公开(公告)日：2018-08-14

申请号：US14967153

申请日：2015-12-11

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Shu-Ming Chang ,  Tsang-Yu Liu ,  Hsing-Lung Shen

IPC: G06K9/00 ,  H01L21/48 ,  H01L23/498 ,  G06F3/041

Abstract: A chip package includes a substrate, a capacitive sensing layer and a computing chip. The substrate has a first surface and a second surface opposite to the first surface, and the capacitive sensing layer is disposed above the second surface and having a third surface opposite to the second surface, which the capacitive sensing layer includes a plurality of capacitive sensing electrodes and a plurality of metal wires. The capacitive sensing electrodes are on the second surface, and the metal wires are on the capacitive sensing electrodes. The computing chip is disposed above the third surface and electrically connected to the capacitive sensing electrodes.

公开(公告)号：US09997473B2

公开(公告)日：2018-06-12

申请号：US15409289

申请日：2017-01-18

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Tsang-Yu Liu ,  Chia-Sheng Lin ,  Chaung-Lin Lai

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/52 ,  H01L21/54 ,  H01L23/18 ,  H01L23/055 ,  H01L21/48

CPC classification number: H01L23/562 ,  H01L21/4817 ,  H01L21/52 ,  H01L21/54 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/055 ,  H01L23/18 ,  H01L23/3114 ,  H01L23/522 ,  H01L24/16 ,  H01L25/065 ,  H01L27/14618 ,  H01L27/14687 ,  H01L2224/16237

Abstract: A chip package including a substrate is provided. The substrate has a first surface and a second surface opposite thereto. The substrate includes a sensing or device region which is adjacent to the first surface. A recess is in the substrate. The recess extends from the second surface towards the first surface, and vertically overlaps the sensing or device region. A redistribution layer is electrically connected to the sensing or device region, and extends from the second surface into the recess. A method of forming the chip package is also provided.

公开(公告)号：US09685354B2

公开(公告)日：2017-06-20

申请号：US14676478

申请日：2015-04-01

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Tsang-Yu Liu ,  Chia-Sheng Lin ,  Yi-Ming Chang

IPC: B26D1/09 ,  H01L21/67 ,  H01L21/683 ,  B26D7/18

CPC classification number: H01L21/67092 ,  B26D1/095 ,  B26D7/1863 ,  H01L21/6838 ,  Y10T83/0267 ,  Y10T225/10 ,  Y10T225/12 ,  Y10T225/364

Abstract: An embodiment of this invention provides a separation apparatus for separating a stacked article, such as a semiconductor chip package with sensing functions, comprising a substrate and a cap layer formed on the substrate. The separation apparatus comprises a vacuum nozzle head including a suction pad having a top surface and a bottom surface, a through hole penetrating the top surface and the bottom surface of the suction pad, and a hollow vacuum pipe connecting the through hole to a vacuum pump; a stage positing under the vacuum nozzle head and substantially aligning with the suction pad; a control means coupling to the vacuum nozzle head to lift upward or lower down the vacuum nozzle head; and a first cutter comprising a first cutting body and a first knife connecting to the first cutting body. The cap layer is pressed against by the bottom surface of the suction pad and sucked by the suction pad of the vacuum nozzle head after the vacuum pump begins to vacuum the air within the hollow vacuum pipe and the through hole. Then, the first cutter cuts into the interface between the substrate and the cap layer, and the cap lay is separated from the substrate by the suction force of the vacuum nozzle head and the lift force generated by the upward movement of the vacuum nozzle head.

公开(公告)号：US09653422B2

公开(公告)日：2017-05-16

申请号：US14673657

申请日：2015-03-30

Applicant: XINTEC INC.

Inventor： Chia-Lun Shen ,  Yi-Ming Chang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/306 ,  H01L21/48

CPC classification number: H01L24/32 ,  H01L21/30604 ,  H01L21/48 ,  H01L21/78 ,  H01L24/05 ,  H01L24/09 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/8389 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/12042 ,  H01L2924/37001 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A method for forming a chip package is provided. The method includes providing a first substrate and a second substrate. The first substrate is attached onto the second substrate by an adhesive layer. A first opening is formed to penetrate the first substrate and the adhesive layer and separate the first substrate and the adhesive layer into portions. A chip package formed by the method is also provided.

公开(公告)号：US09640488B2

公开(公告)日：2017-05-02

申请号：US15008202

申请日：2016-01-27

Applicant: XINTEC INC.

Inventor： Yi-Min Lin ,  Yi-Ming Chang ,  Shu-Ming Chang ,  Yen-Shih Ho ,  Tsang-Yu Liu ,  Chia-Ming Cheng

IPC: H01L23/552 ,  H01L21/48 ,  H01L21/78 ,  H01L29/06 ,  H01L23/00 ,  H01L23/544 ,  H01L25/065

CPC classification number: H01L23/552 ,  H01L21/4814 ,  H01L21/78 ,  H01L23/544 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2223/5446 ,  H01L2224/02313 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/0239 ,  H01L2224/03614 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/451 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/4847 ,  H01L2224/92 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10157 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01078 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2924/01022 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2924/014 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed over the first surface and extending into the first recess and/or the second recess; an insulating layer positioned between the wire layer and the semiconductor substrate; and a metal light shielding layer disposed over the first surface and having at least one hole, wherein a shape of the at least one hole is a quadrangle.

公开(公告)号：US09613904B2

公开(公告)日：2017-04-04

申请号：US15140289

申请日：2016-04-27

Applicant: XINTEC INC.

Inventor： Yu-Tung Chen ,  Chien-Min Lin ,  Chuan-Jin Shiu ,  Chih-Wei Ho ,  Yen-Shih Ho

IPC: H01L21/4763 ,  H01L21/44 ,  H01L23/04 ,  H01L23/52 ,  H01L23/528 ,  H01L21/027 ,  H01L23/522 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/5283 ,  H01L21/0271 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0345 ,  H01L2224/0557

Abstract: A semiconductor structure includes a first substrate, a second substrate, a dam layer, a photoresist layer, and a conductive layer. The first substrate has a conductive pad. The second substrate has a through via, a sidewall surface surrounding the through via, a first surface, and a second surface opposite to the first surface. The through via penetrates through the first and second surfaces. The conductive pad is aligned with the through via. The dam layer is located between the first substrate and the second surface. The dam layer protrudes toward the through via. The photoresist layer is located on the first surface, the sidewall surface, the dam layer protruding toward the through via, and between the conductive pad and the dam layer protruding toward the through via. The conductive layer is located on the photoresist layer and the conductive pad.

公开(公告)号：US09601460B2

公开(公告)日：2017-03-21

申请号：US14618413

申请日：2015-02-10

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Tsang-Yu Liu ,  Chia-Sheng Lin ,  Chia-Ming Cheng ,  Shu-Ming Chang ,  Tzu-Wen Tseng

IPC: H01L23/06 ,  H01L23/00 ,  H01L23/31 ,  H01L29/06 ,  H01L23/525

CPC classification number: H01L24/94 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L29/0657 ,  H01L2224/0224 ,  H01L2224/02245 ,  H01L2224/02255 ,  H01L2224/0226 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/06165 ,  H01L2224/10135 ,  H01L2224/10145 ,  H01L2224/94 ,  H01L2924/3512 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/0665

Abstract: A chip package including a semiconductor substrate is provided. A recess is in the semiconductor substrate and adjoins a side edge of the semiconductor substrate, wherein the semiconductor substrate has at least one spacer protruding from the bottom of the recess. A conducting layer is disposed on the semiconductor substrate and extends into the recess.

公开(公告)号：US09437478B2

公开(公告)日：2016-09-06

申请号：US14339360

申请日：2014-07-23

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Tsang-Yu Liu ,  Shu-Ming Chang ,  Yu-Lung Huang ,  Chao-Yen Lin ,  Wei-Luen Suen ,  Chien-Hui Chen ,  Ho-Yin Yiu

IPC: H01L21/768 ,  H01L23/31 ,  H01L21/56 ,  G06K9/00 ,  H01L23/00 ,  H01L23/525 ,  H01L23/532

CPC classification number: H01L21/76802 ,  G06K9/00053 ,  H01L21/561 ,  H01L21/76877 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/02166 ,  H01L2224/02381 ,  H01L2224/024 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/06135 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48669 ,  H01L2224/48687 ,  H01L2224/4869 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A chip package including a chip is provided. The chip includes a sensing region or device region adjacent to an upper surface of the chip. A sensing array is located in the sensing region or device region and includes a plurality of sensing units. A plurality of first openings is located in the chip and correspondingly exposes the sensing units. A plurality of conductive extending portions is disposed in the first openings and is electrically connected to the sensing units, wherein the conductive extending portions extend from the first openings onto the upper surface of the chip. A method for forming the chip package is also provided.

Abstract translation: 提供了包括芯片的芯片封装。 芯片包括与芯片的上表面相邻的感测区域或器件区域。 感测阵列位于感测区域或设备区域中并且包括多个感测单元。 多个第一开口位于芯片中并且相应地暴露感测单元。 多个导电延伸部分设置在第一开口中并且电连接到感测单元，其中导电延伸部分从第一开口延伸到芯片的上表面上。 还提供了一种用于形成芯片封装的方法。