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    Semiconductor structure having stage difference surface and manufacturing method thereof
    11.
    发明授权
    Semiconductor structure having stage difference surface and manufacturing method thereof 有权
    具有台阶差的半导体结构及其制造方法

    公开(公告)号：US09275963B2

    公开(公告)日：2016-03-01

    申请号：US14199640

    申请日：2014-03-06

    Applicant: XINTEC INC.

    Inventor： Yung-Tai Tsai ,  Shu-Ming Chang ,  Chun-Wei Chang ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Yen-Shih Ho

    IPC: H01L23/00 ,  H01L23/31 ,  H01L21/78

    CPC classification number: H01L24/05 ,  H01L21/78 ,  H01L23/3185 ,  H01L23/3192 ,  H01L24/03 ,  H01L2224/02371 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/94 ,  H01L2924/10156 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/00014

    Abstract: A semiconductor structure includes a wafer, at least one nonmetal oxide layer, a pad, a passivation layer, an isolation layer, and a conductive layer. The wafer has a first surface, a second surface, a third surface, a first stage difference surface connected between the second and third surfaces, and a second stage difference surface connected between the first and third surfaces. The nonmetal oxide layer is located on the first surface of the wafer. The pad is located on the nonmetal oxide layer and electrically connected to the wafer. The passivation layer is located on the nonmetal oxide layer. The isolation layer is located on the passivation layer, nonmetal oxide layer, the first, second and third surfaces of the wafer, and the first and second stage difference surfaces of the wafer. The conductive layer is located on the isolation layer and electrically contacts the pad.

    Abstract translation: 半导体结构包括晶片，至少一个非金属氧化物层，焊盘，钝化层，隔离层和导电层。 晶片具有连接在第二和第三表面之间的第一表面，第二表面，第三表面，第一阶段差异表面以及连接在第一和第三表面之间的第二阶段差异表面。 非金属氧化物层位于晶片的第一表面上。 垫位于非金属氧化物层上并电连接到晶片。 钝化层位于非金属氧化物层上。 隔离层位于钝化层，非金属氧化物层，晶片的第一，第二和第三表面以及晶片的第一和第二级差分表面上。 导电层位于隔离层上并电接触焊盘。

    Chip package and method of manufacturing the same
    12.
    发明授权
    Chip package and method of manufacturing the same 有权
    芯片封装及其制造方法

    公开(公告)号：US09269837B2

    公开(公告)日：2016-02-23

    申请号：US14682888

    申请日：2015-04-09

    Applicant: XINTEC INC.

    Inventor： Tsang-Yu Liu ,  Shu-Ming Chang ,  Po-Han Lee

    IPC: H01L23/00 ,  H01L31/0203 ,  H01L31/18 ,  H01L31/02 ,  H01L23/31 ,  H01L23/48

    CPC classification number: H01L31/0203 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/12 ,  H01L24/13 ,  H01L31/02005 ,  H01L31/18 ,  H01L2224/131 ,  H01L2224/73253 ,  Y02P70/521 ,  H01L2924/014

    Abstract: A chip package includes semiconductor chips, inner spacers, cavities, conductive portions and solder balls. The semiconductor chip has at least an electronic component and at least an electrically conductive pad disposed on an upper surface thereof. The conductive pad is arranged abreast to one side of the electronic component and electrically connected thereto. The cavities open to a lower surface of the semiconductor chip and extend toward the upper surface to expose the conductive pad on the upper surface. The conductive portions fill the cavities from the lower surface and electrically connected the to conductive pad. The solder balls are disposed on the lower surface and electrically connected to the conductive portions. A gap is created between an outer wall of the inner spacers and an edge of the semiconductor chip.

    Abstract translation: 芯片封装包括半导体芯片，内部间隔件，空腔，导电部分和焊球。 半导体芯片至少具有电子部件，并且至少设置在其上表面上的导电焊盘。 导电焊盘与电子部件的一侧并排设置并与之电连接。 空腔通向半导体芯片的下表面并朝向上表面延伸以暴露上表面上的导电焊盘。 导电部分从下表面填充空腔并电连接到导电垫。 焊球设置在下表面上并电连接到导电部分。 在内隔板的外壁和半导体芯片的边缘之间产生间隙。

    Semiconductor package and fabrication method thereof
    14.
    发明授权
    Semiconductor package and fabrication method thereof 有权
    半导体封装及其制造方法

    公开(公告)号：US08928098B2

    公开(公告)日：2015-01-06

    申请号：US13714218

    申请日：2012-12-13

    Applicant: Xintec Inc.

    Inventor： Hung-Jen Lee ,  Shu-Ming Chang ,  Tsang-Yu Liu ,  Yen-Shih Ho

    IPC: B81B7/00 ,  B81C1/00

    CPC classification number: B81B7/007 ,  B81C1/0023 ,  B81C1/00301

    Abstract: A semiconductor package includes: a chip having a first portion and a second portion disposed on the first portion, wherein the second portion has at least a through hole therein for exposing a portion of the first portion, and the first portion and/or the second portion has a MEMS; and an etch stop layer formed between the first portion and the second portion and partially exposed through the through hole of the second portion. The invention allows an electronic element to be received in the through hole so as for the semiconductor package to have integrated functions of the MEMS and the electronic element. Therefore, the need to dispose the electronic element on a circuit board as in the prior art can be eliminated, thereby saving space on the circuit board.

    Abstract translation: 半导体封装包括：具有第一部分和设置在第一部分上的第二部分的芯片，其中第二部分至少在其中具有用于暴露第一部分的一部分的通孔，以及第一部分和/或第二部分 部分具有MEMS; 以及形成在所述第一部分和所述第二部分之间并且部分地暴露于所述第二部分的通孔的蚀刻停止层。 本发明允许电子元件被容纳在通孔中，以便半导体封装具有MEMS和电子元件的集成功能。 因此，可以消除如现有技术那样将电子元件配置在电路板上，从而节省了电路板上的空间。

    Power MOSFET package
    15.
    发明授权
    Power MOSFET package 有权
    功率MOSFET封装

    公开(公告)号：US08766431B2

    公开(公告)日：2014-07-01

    申请号：US13828537

    申请日：2013-03-14

    Applicant: Xintec Inc.

    Inventor： Baw-Ching Perng ,  Ying-Nan Wen ,  Shu-Ming Chang ,  Ching-Yu Ni ,  Yun-Ji Hsieh ,  Wei-Ming Chen ,  Chia-Lun Tsai ,  Chia-Ming Cheng

    IPC: H01L23/04

    CPC classification number: H01L29/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/492 ,  H01L24/13 ,  H01L24/16 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/7802 ,  H01L29/7809 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01021 ,  H01L2924/13091 ,  H01L2224/05599 ,  H01L2224/05099

    Abstract: A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrate and the terminals.

    Abstract translation: 功率MOSFET封装包括具有相反的第一和第二表面的半导体衬底，具有第一导电类型，并形成漏极区，从第一表面向下延伸并具有第二导电类型的掺杂区，掺杂区中的源极区 并且具有第一导电类型，覆盖或掩埋在第一表面下方的栅极，其中栅极电介质层位于栅极和半导体衬底之间，覆盖半导体衬底的第一导电结构，具有第一端子，并且电连接漏极 区域，覆盖半导体衬底的第二导电结构，具有第二端子，并且电连接源极区域，覆盖半导体衬底的第三导电结构，具有第三端子和电连接栅极，其中第一，第二， 并且第三端子基本上共面，并且第三端子之间的保护层 e半导体衬底和端子。

    Chip package and method for forming the same
    17.
    发明授权
    Chip package and method for forming the same 有权

    公开(公告)号：US10446504B2

    公开(公告)日：2019-10-15

    申请号：US15980577

    申请日：2018-05-15

    Applicant: XINTEC INC.

    Inventor： Chia-Ming Cheng ,  Po-Han Lee ,  Wei-Chung Yang ,  Kuan-Jung Wu ,  Shu-Ming Chang

    IPC: H01L23/52 ,  H01L23/00 ,  H01L25/16 ,  H01L21/56 ,  H01L23/31 ,  H01L23/04 ,  H01L27/146

    Abstract: A chip package is provided. A first bonding structure is disposed on a first redistribution layer (RDL). A first chip includes a sensing region and a conductive pad that are adjacent to an active surface. The first chip is bonded onto the first RDL through the first bonding structure. The first bonding structure is disposed between the conductive pad and the first RDL. A molding layer covers the first RDL and surrounds the first chip. A second RDL is disposed on the molding layer and the first chip and is electrically connected to the first RDL. A second chip is stacked on a non-active surface of the first chip and is electrically connected to the first chip through the second RDL, the first RDL, and the first bonding structure. A method of forming the chip package is also provided.

    Touch panel-sensing chip package module complex and a manufacturing method thereof
    18.
    发明授权
    Touch panel-sensing chip package module complex and a manufacturing method thereof 有权

    公开(公告)号：US10318784B2

    公开(公告)日：2019-06-11

    申请号：US15177143

    申请日：2016-06-08

    Applicant: XINTEC INC.

    Inventor： Shu-Ming Chang ,  Tsang-Yu Liu ,  Yen-Shih Ho

    IPC: G06K9/00 ,  G06F3/041

    Abstract: This invention provides a touch panel-sensing chip package module complex, comprising: a touch panel with a first top surface and a first bottom surface opposite to each other, wherein the first bottom surface having a first cavity with a bottom wall surrounded by a sidewall; a color layer formed on the bottom wall and the first bottom surface adjacent to the cavity; and a chip scale sensing chip package module bonded to the cavity by the color layer formed on the bottom wall of the cavity.

    Sensing module and method for forming the same
    20.
    发明授权
    Sensing module and method for forming the same 有权

    公开(公告)号：US09711425B2

    公开(公告)日：2017-07-18

    申请号：US15237287

    申请日：2016-08-15

    Applicant: XINTEC INC.

    Inventor： Shu-Ming Chang ,  Po-Chang Huang ,  Tsang-Yu Liu ,  Yu-Lung Huang ,  Chi-Chang Liao

    IPC: H01L23/31 ,  G06K9/00 ,  H01L23/48

    CPC classification number: H01L23/3121 ,  G06K9/00013 ,  G06K9/0002 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/481 ,  H01L2224/11

    Abstract: A sensing module is provided. The sensing module includes a sensing device. The sensing device includes a first substrate having a first surface and a second surface opposite thereto. The sensing device also includes a sensing region adjacent to the first surface and a conducting pad on the first surface. The sensing device further includes a redistribution layer on the second surface and electrically connected to the conducting pad. The sensing module also includes a second substrate and a cover plate bonded to the sensing device so that the sensing device is between the second substrate and the cover plate. The conducting pad is electrically connected to the second substrate through the redistribution layer. The sensing module further includes an encapsulating layer filled between the second substrate and the cover plate to surround the sensing device.

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