公开(公告)号：US20170062439A1

公开(公告)日：2017-03-02

申请号：US15347530

申请日：2016-11-09

申请人： QUALCOMM Incorporated

发明人： Niladri Narayan Mojumder ,  Ritu Chaba ,  Ping Liu ,  Stanley Seungchul Song ,  Zhongze Wang ,  Choh Fei Yeap

IPC分类号： H01L27/11 ,  H01L23/528 ,  G11C11/419 ,  H01L21/768 ,  H01L21/3213 ,  H01L27/02 ,  H01L23/522

CPC分类号： H01L27/1104 ,  G11C8/14 ,  G11C8/16 ,  G11C11/418 ,  G11C11/419 ,  H01L21/3213 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11

摘要： An apparatus includes a first metal layer coupled to a bit cell. The apparatus also includes a third metal layer including a write word line that is coupled to the bit cell. The apparatus further includes a second metal layer between the first metal layer and the third metal layer. The second metal layer includes two read word lines coupled to the bit cell.

摘要翻译： 一种装置包括耦合到位单元的第一金属层。 该装置还包括第三金属层，其包括耦合到位单元的写入字线。 该装置还包括在第一金属层和第三金属层之间的第二金属层。 第二金属层包括耦合到位单元的两个读字线。

公开(公告)号：US20170040229A1

公开(公告)日：2017-02-09

申请号：US15301488

申请日：2014-05-21

申请人： Mitsubishi Electric Corporation

发明人： Takuichiro SHITOMI ,  Kazuhisa KOGA ,  Satoshi RITTAKU

IPC分类号： H01L21/66 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/768 ,  H01L21/67 ,  H01L21/28

CPC分类号： H01L22/12 ,  H01L21/02274 ,  H01L21/205 ,  H01L21/28008 ,  H01L21/3213 ,  H01L21/67248 ,  H01L21/76801

摘要： A semiconductor device manufacturing method includes an element forming step of forming an clement structure on a front surface of a substrate and forming a back structure on a back surface of the substrate, and a film forming step of performing film forming on a front surface of the element structure while measuring the temperature of the substrate by using a radiation thermometer that applies infrared rays of a wavelength λi to the back structure to obtain an infrared emissivity of the substrate. The back structure has a first layer exposed to the outside and a second layer in contact with the first layer, the refractive index of the second layer being smaller than that of the first layer, and the layer thickness of the first layer is set in a range from (2n−1)λi/8 to (2n+1)λi/8, with n being a positive even number.

摘要翻译： 半导体器件制造方法包括：元件形成步骤，在基板的前表面上形成元件结构，并在基板的背面形成背面结构;以及成膜步骤，在所述基板的表面上进行成膜 元件结构，同时通过使用将波长λi的红外线施加到背面结构的辐射温度计来测量衬底的温度，以获得衬底的红外发射率。 背面结构具有暴露于外部的第一层和与第一层接触的第二层，第二层的折射率小于第一层的折射率，第一层的层厚度设定为 范围从（2n-1）λi/ 8到（2n + 1）λi/ 8，其中n是正偶数。

公开(公告)号：US09520339B2

公开(公告)日：2016-12-13

申请号：US14615400

申请日：2015-02-05

申请人： Kabushiki Kaisha Toshiba

发明人： Akiko Nomachi

IPC分类号： H01L21/76 ,  H01L23/48 ,  H01L21/3065 ,  H01L21/768 ,  H01L23/00 ,  H01L21/3213 ,  H01L29/06

CPC分类号： H01L23/481 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/76898 ,  H01L24/10 ,  H01L24/11 ,  H01L29/0649 ,  H01L2924/13091 ,  H01L2924/00

摘要： According to one embodiment, a semiconductor device includes a semiconductor substrate having a first surface and a second surface, and having a LSI on the first surface of the semiconductor substrate, a first insulating layer with an opening, the first insulating layer provided on the first surface of the semiconductor substrate, a conductive layer on the opening, the conductive layer being connected to the LSI, and a via extending from a second surface of the semiconductor substrate to the conductive layer through the opening, the via having a size larger than a size of the opening in a range from the second surface to a first interface between the semiconductor substrate and the first insulating layer, and having a size equal to the size of the opening in the opening.

摘要翻译： 根据一个实施例，半导体器件包括具有第一表面和第二表面的半导体衬底，并且在半导体衬底的第一表面上具有LSI，具有开口的第一绝缘层，第一绝缘层设置在第一表面 半导体衬底的表面，开口上的导电层，导电层连接到LSI，以及通过该开口从半导体衬底的第二表面延伸到导电层的通孔，通孔的尺寸大于 从第二表面到半导体衬底和第一绝缘层之间的第一界面的范围内的开口尺寸，并且具有与开口中的开口尺寸相等的尺寸。

公开(公告)号：US09490129B2

公开(公告)日：2016-11-08

申请号：US14272952

申请日：2014-05-08

申请人： GLOBALFOUNDRIES, Inc.

发明人： Xiang Hu ,  Huang Liu

IPC分类号： H01L21/336 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/311 ,  H01L27/088

CPC分类号： H01L21/28123 ,  H01L21/28035 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/31053 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3213 ,  H01L21/32133 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/49 ,  H01L29/4916 ,  H01L29/66 ,  H01L29/66553 ,  H01L29/6681

摘要： Integrated circuits with improved gate structures and methods for fabricating integrated circuits with improved gate structures are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with fin structures. A gate-forming material is deposited over the semiconductor substrate and fin structures. The method includes performing a first etch process to etch the gate-forming material to form a gate line having a first side and a second side. The first side and second side of the gate line are bounded with material. The method includes performing a second etch process to etch a portion of the gate line bound by the material to separate the gate line into adjacent gate structures and to define a tip-to-tip distance between the adjacent gate structures.

摘要翻译： 提供了具有改进的栅极结构的集成电路和用于制造具有改进的栅极结构的集成电路的方法。 在一个实施例中，制造集成电路的方法包括提供具有鳍结构的半导体衬底。 栅极形成材料沉积在半导体衬底和鳍结构上。 该方法包括执行第一蚀刻工艺以蚀刻栅极形成材料以形成具有第一侧和第二侧的栅极线。 栅极线的第一侧和第二侧与材料有界。 该方法包括执行第二蚀刻工艺以蚀刻由材料限定的栅极线的一部分，以将栅极线分离成相邻的栅极结构并且限定相邻栅极结构之间的尖端到尖端的距离。

公开(公告)号：US20160320706A1

公开(公告)日：2016-11-03

申请号：US15189311

申请日：2016-06-22

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chin-Hsiung HSU ,  Huang-Yu CHEN ,  Tsong-Hua OU ,  Wen-Hao CHEN

IPC分类号： G03F7/20 ,  G06F17/50 ,  G03F1/70 ,  H01L21/3213

CPC分类号： G03F7/2022 ,  G03F1/70 ,  G06F17/5068 ,  H01L21/3213 ,  H05K3/0005 ,  H05K3/0082 ,  H05K3/06 ,  H05K3/068 ,  H05K2201/09781 ,  H05K2203/0557 ,  H05K2203/1476 ,  Y10T29/49156

摘要： A method includes patterning a layer over a substrate with a first metal pattern; using a cut mask in a first position relative to the substrate to perform a first cut patterning for removing material from a first region within the first pattern; and using the same cut mask to perform a second cut patterning while in a second position relative to the same layer over the substrate, for removing material from a second region in a second metal pattern of the same layer over the substrate.

摘要翻译： 一种方法包括用第一金属图案在衬底上图案化层; 在相对于所述基板的第一位置使用切割掩模，以执行用于从所述第一图案内的第一区域去除材料的第一切割图案; 并且使用相同的切割掩模在相对于衬底上的相同层的第二位置执行第二切割图案，用于从衬底上的相同层的第二金属图案中的第二区域去除材料。

公开(公告)号：US09443957B1

公开(公告)日：2016-09-13

申请号：US14656371

申请日：2015-03-12

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Joel P. de Souza ,  Bahman Hekmatshoartabari ,  Jeehwan Kim ,  Siegfried L. Maurer ,  Devendra K. Sadana

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/225 ,  H01L29/423 ,  H01L21/3213 ,  H01L29/08

CPC分类号： H01L21/283 ,  A23C9/123 ,  A23C9/1315 ,  A23C11/08 ,  H01L21/2254 ,  H01L21/28114 ,  H01L21/30604 ,  H01L21/3213 ,  H01L21/32131 ,  H01L21/32133 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/66446 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/78

摘要： A method for forming a semiconductor device includes patterning a gate conductor, formed on a substrate, and a two-dimensional material formed on the gate conductor. Recesses are formed adjacent to the gate conductor in the substrate, and a doped layer is deposited in the recesses and over a top of the two-dimensional material. Tape is adhered to the doped layer on top of the two-dimensional material. The tape is removed to exfoliate the doped layer from the top of the two-dimensional material to form source and drain regions in the recesses.

摘要翻译： 一种用于形成半导体器件的方法包括图案化形成在基底上的栅极导体和形成在栅极导体上的二维材料。 在衬底中形成与栅极导体相邻的凹陷，并且掺杂层沉积在凹部中并在二维材料的顶部上。 胶带粘附在二维材料顶部的掺杂层上。 去除带以从二维材料的顶部剥离掺杂层以在凹槽中形成源区和漏区。

公开(公告)号：US20160172209A1

公开(公告)日：2016-06-16

申请号：US15047793

申请日：2016-02-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wen-Kuei Liu ,  Teng-Chun Tsai ,  Kuo-Yin Lin ,  Shen-Nan Lee ,  Yu-Wei Chou ,  Kuo-Cheng Lien ,  Chang-Sheng Lin ,  Chih-Chang Hung ,  Yung-Cheng Lu

IPC分类号： H01L21/3105 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/027 ,  H01L21/28

CPC分类号： H01L21/31055 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/28008 ,  H01L21/31058 ,  H01L21/31116 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/3213 ,  H01L21/32139 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66545

摘要： An IC device manufacturing process effectuates a planar recessing of material that initially varies in height across a substrate. The method includes forming a polymer coating, CMP to form a planar surface, then plasma etching to effectuate a planar recessing of the polymer coating. The material can be recessed together with the polymer coating, or subsequently with the recessed polymer coating providing a mask. Any of the material above a certain height is removed. Structures that are substantially below that certain height can be protected from contamination and left intact. The polymer can be a photoresist. The polymer can be provided with suitable adhesion and uniformity for the CMP process through a two-step baking process and by exhausting the baking chamber from below the substrate.

公开(公告)号：US09337353B2

公开(公告)日：2016-05-10

申请号：US14825801

申请日：2015-08-13

申请人： SK hynix Inc.

发明人： Kyung-Sik Mun

IPC分类号： H01L21/28 ,  H01L29/792 ,  H01L29/66 ,  H01L21/76 ,  H01L27/115 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213

CPC分类号： H01L29/792 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/28282 ,  H01L21/31105 ,  H01L21/3213 ,  H01L21/76 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： A semiconductor device and a method of manufacturing the same. The semiconductor device includes a channel, a gate, and a memory layer is interposed between the channel and the gate. The memory layer includes a tunnel insulating layer adjacent to the channel, a charge blocking layer adjacent to the gate, and a charge storing layer interposed between the tunnel insulating layer and the charge blocking layer. The tunnel insulating layer includes a first insulating layer adjacent to the channel and an air layer interposed between the first insulating layer and the charge storing layer.

公开(公告)号：US20160013262A1

公开(公告)日：2016-01-14

申请号：US14326659

申请日：2014-07-09

申请人： GLOBALFOUNDRIES Inc.

发明人： Luke ENGLAND ,  Mahesh Anant BHATKAR ,  Wanbing YI ,  Juan Boon TAN

IPC分类号： H01L49/02 ,  H01L21/311 ,  H01L21/78 ,  H01L21/3213 ,  H01L21/321 ,  H01L21/324 ,  H01L21/033 ,  H01L21/288

CPC分类号： H01L28/10 ,  H01L21/0335 ,  H01L21/2885 ,  H01L21/31058 ,  H01L21/31127 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/3213 ,  H01L21/324 ,  H01L21/78 ,  H01L23/49822 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

摘要： Wafer-level methods of forming circuit elements, such as multilayer inductors or transformers, are provided. The methods include, for instance: forming, in at least one layer above a substrate, at least one conductive portion of the circuit element; providing an uncured polymer-dielectric material surrounding, at least in part, and overlying the conductive portion(s) of the element; partially curing the polymer-dielectric material to obtain a partially-hardened, polymer-dielectric material; and polishing the partially-hardened, polymer-dielectric material down to the conductive portion(s). The polishing planarizes the partially-hardened, polymer-dielectric material and exposes an upper surface of the conductive portion(s) to facilitate forming at least one other conductive portion of the element above and in electrical contact with the conductive portion(s). After polishing, curing of the polymer-dielectric material is completed. In one embodiment, the conductive portion(s) and the other conductive portion(s) define, at least in part, a conductive coil(s) of the element.

摘要翻译： 提供了形成诸如多层电感器或变压器的电路元件的晶片级方法。 所述方法包括例如：在衬底上的至少一层中形成电路元件的至少一个导电部分; 提供至少部分地覆盖所述元件的导电部分并且覆盖所述元件的导电部分的未固化的聚合物 - 电介质材料; 部分固化聚合物 - 电介质材料以获得部分硬化的聚合物电介质材料; 并将部分硬化的聚合物电介质材料抛光至导电部分。 抛光使部分硬化的聚合物 - 电介质材料平坦化并且暴露导电部分的上表面，以便于在导电部分上方形成与元件电连接的元件的至少一个其它导电部分。 抛光后，完成聚合物 - 电介质材料的固化。 在一个实施例中，导电部分和另一个导电部分至少部分地限定该元件的导电线圈。

公开(公告)号：US20160005772A1

公开(公告)日：2016-01-07

申请号：US14852976

申请日：2015-09-14

申请人： BOE TECHNOLOGY GROUP CO., LTD. ,  HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.

发明人： Bozhu ZHOU ,  Mingji BAI ,  Binbin CAO ,  Na ZHAO ,  Wenlong WANG ,  Yijun WANG

IPC分类号： H01L27/12 ,  H01L21/3213 ,  H01L29/423

CPC分类号： H01L27/1259 ,  H01L21/3213 ,  H01L27/124 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/458 ,  H01L33/0041

摘要： Embodiments of the invention provide an array substrate, a manufacturing method thereof and a display device. The array substrate comprises: a base substrate; a gate line and a gate electrode formed on the base substrate; a gate insulating layer formed on the gate line and the gate electrode; a source electrode, a drain electrode and a pixel electrode formed on the gate insulating layer, wherein the pixel electrode is directly connected to the drain electrode; and an active layer formed on the gate insulating layer, the source electrode and the drain electrode.

摘要翻译： 本发明的实施例提供阵列基板，其制造方法和显示装置。 阵列基板包括：基底; 形成在基底基板上的栅极线和栅电极; 形成在栅极线和栅电极上的栅极绝缘层; 形成在所述栅极绝缘层上的源电极，漏电极和像素电极，其中所述像素电极直接连接到所述漏电极; 以及形成在栅极绝缘层，源电极和漏电极上的有源层。