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    FLIPPED DIE STACK ASSEMBLIES WITH LEADFRAME INTERCONNECTS
    213.
    发明申请
    FLIPPED DIE STACK ASSEMBLIES WITH LEADFRAME INTERCONNECTS 有权
    带有LEADFRAME INTERCONNECTS的襟翼堆叠组件

    公开(公告)号：US20170018485A1

    公开(公告)日：2017-01-19

    申请号：US15209034

    申请日：2016-07-13

    Applicant: Invensas Corporation

    Inventor： Ashok S. Prabhu ,  Rajesh Katkar ,  Liang Wang ,  Cyprian Emeka Uzoh

    IPC: H01L23/495 ,  H01L25/065 ,  H01L21/48 ,  H01L23/498

    CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/49541 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/02371 ,  H01L2224/04105 ,  H01L2224/18

    Abstract: A microelectronic assembly includes a stack of microelectronic elements, e.g., semiconductor chips, each having a front surface defining a respective plane of a plurality of planes. A leadframe interconnect joined to a contact at a front surface of each chip may extend to a position beyond the edge surface of the respective microelectronic element. The chip stack is mounted to support element at an angle such that edge surfaces of the chips face a major surface of the support element that defines a second plane that is transverse to, i.e., not parallel to the plurality of parallel planes. The leadframe interconnects are electrically coupled at ends thereof to corresponding contacts at a surface of the support element.

    Abstract translation: 微电子组件包括一组微电子元件，例如半导体芯片，每个半导体芯片具有限定多个平面的相应平面的前表面。 连接到每个芯片的前表面处的触点的引线框互连可以延伸到超过相应微电子元件的边缘表面的位置。 芯片堆叠以一定角度安装到支撑元件，使得芯片的边缘表​​面面向支撑元件的主表面，该主表面限定横向于，即不平行于多个平行平面的第二平面。 引线框互连在其端部电耦合到支撑元件的表面处的相应触点。

    THROUGH-DIELECTRIC-VIAS (TDVs) FOR 3D INTEGRATED CIRCUITS IN SILICON
    215.
    发明申请
    THROUGH-DIELECTRIC-VIAS (TDVs) FOR 3D INTEGRATED CIRCUITS IN SILICON 审中-公开
    用于三维集成电路的通用电介质（TDV）

    公开(公告)号：US20160343613A1

    公开(公告)日：2016-11-24

    申请号：US15157197

    申请日：2016-05-17

    Applicant: Invensas Corporation

    Inventor： Cyprian Emeka Uzoh

    IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

    CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L23/5329 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06544

    Abstract: Through-dielectric-vias (TDVs) for 3D integrated circuits in silicon are provided. Example structures and processes fabricate conductive vertical pillars for an integrated circuit assembly in a volume of dielectric material instead of in silicon. For example, a block of a silicon substrate may be removed and replaced with dielectric material, and then a plurality of the conductive pillars can be fabricated through the dielectric block. The through-dielectric-vias are shielded from devices and from each other by an intervening thickness of the dielectric sufficient to reduce noise, signal coupling, and frequency losses. The through-dielectric-vias can provide improved stress management and reduced keep-out-zones, reduced via-to-via and via-to-device coupling because of relatively large dielectric spacing and low-k dielectrics that can be used, reduced parasitic capacitance, faster switching speeds, lower heat dissipation requirements, lower production costs, easy miniaturization that is scalable to large assemblies and interposers, and high performance stacked assemblies.

    Abstract translation: 提供了用于硅中3D集成电路的通电介质通孔（TDV）。 示例性结构和工艺制造用于介电材料体积中的集成电路组件的导电垂直柱而不是硅。 例如，可以移除硅衬底的块并用介电材料代替，然后可以通过介电块制造多个导电柱。 通过电介质通孔被屏蔽并且彼此隔开介质的中间厚度足以减少噪声，信号耦合和频率损失。 通过电介质通孔可以提供改进的应力管理和减少的保持区域，减小的通孔到通孔和通孔到器件耦合，因为可以使用相对较大的电介质间隔和低k电介质，减少寄生 电容，更快的开关速度，更低的散热要求，更低的生产成本，易于小型化，可扩展到大型组件和插入件以及高性能堆叠组件。

    Low cost interposer and method of fabrication
    218.
    发明授权
    Low cost interposer and method of fabrication 有权
    低成本插入器和制造方法

    公开(公告)号：US09455162B2

    公开(公告)日：2016-09-27

    申请号：US13830279

    申请日：2013-03-14

    Applicant: Invensas Corporation

    Inventor： Cyprian Emeka Uzoh

    IPC: H01L21/44 ,  H01L21/64 ,  H01L23/498 ,  H01L21/48

    CPC classification number: H01L21/64 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49861 ,  H01L2924/0002 ,  H01L2924/19107 ,  H01L2924/00

    Abstract: A method for making an interposer is provided. A conductive layer is formed by contacting a replicate such that a shape of a surface of the conductive layer conforms to a shape of the contacted portion of the replicate. The conductive layer is formed to have a base and a plurality of conductive posts projecting away from the base. Each conductive post is formed to have a post end opposite the base. A dielectric layer is formed to cover the base and to separate adjacent ones of the posts from each other. The posts are for forming vias. Conductive material is removed from the conductive layer to insulate at least one post from at least one other post.

    Abstract translation: 提供了一种制造插入件的方法。 通过使重复接触形成导电层，使得导电层的表面的形状与复制体的接触部分的形状一致。 导电层形成为具有基部和从基部突出的多个导电柱。 每个导电柱形成为具有与基部相对的后端。 形成介电层以覆盖基部并将相邻的柱彼此分开。 这些岗位用于形成通孔。 从导电层移除导电材料，以将至少一个柱与至少一个其他柱绝缘。

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