公开(公告)号：US5534732A

公开(公告)日：1996-07-09

申请号：US567437

申请日：1995-12-04

Applicant: John K. DeBrosse ,  Jenifer E. Lary ,  Edmund J. Sprogis

Inventor： John K. DeBrosse ,  Jenifer E. Lary ,  Edmund J. Sprogis

IPC: H01L21/822 ,  G11C7/18 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/04 ,  H01L27/108 ,  H01L27/10

CPC classification number: H01L27/108 ,  G11C7/18 ,  H01L23/5225 ,  H01L2924/0002 ,  Y10S257/907

Abstract: An interconnection array layout and method are provided for a plurality of paired line conductors of a given length extending principally parallel. A single crossing region traverses the paired line conductors intermediate the given length, wherein the line conductors of each pair of line conductors cross such that inter-pair capacitive coupling is matched. Intra-pair capacitive coupling is avoided by separating the line conductors of each pair of line conductors by two pitches and disposing therebetween a line conductor of a different pair of line conductors. Applications include semiconductor memory arrays, such as DRAM structures, and address/data busses wherein paired true/complement line conductors are employed.

Abstract translation: 为主要平行延伸的给定长度的多个成对线导体提供互连阵列布局和方法。 单个交叉区域穿过给定长度中间的成对线导体，其中每对线路导体的线路导体互相交叉，使得对间电容耦合相匹配。 通过将每对线路导体的线路导体分开两个间距并在其间设置不同对线路导线的线路导体来避免对内电容耦合。 应用包括诸如DRAM结构的半导体存储器阵列，以及使用配对的真/互补线导体的地址/数据总线。

公开(公告)号：US5303196A

公开(公告)日：1994-04-12

申请号：US888226

申请日：1992-05-22

Applicant: Hoo D. Sang ,  Edmund J. Sprogis

Inventor： Hoo D. Sang ,  Edmund J. Sprogis

IPC: G11C11/401 ,  G11C7/06 ,  G11C7/18 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C13/00

CPC classification number: G11C7/18 ,  G11C11/4091 ,  G11C7/06

Abstract: An open bit line memory device and operational method are provided having performance characteristics commensurate with those of folded bit line architecture. The memory device includes a plurality of memory cells in open bit line configuration, at least some of which are interconnected by a bit line. A sense amplifier unit is coupled to the bit line for sensing a developing signal thereon during a predefined bit line signal development interval. The amplifier sets to one of two logical states during a subsequent setting interval. An electrical isolator is employed to decouple the bit line from the sense amplifier during the setting interval so that signal variations on the bit line do not effect the amplifier. Each bit line also has an associated reference voltage line, and the electrical isolator isolates both the bit line and the associated reference voltage line from the sense amplifier during amplifier's setting period.

Abstract translation: 提供了一种开放位线存储器件和操作方法，其具有与折叠位线架构相匹配的性能特征。 存储器件包括开放位线配置的多个存储器单元，其中至少一些由位线互连。 感测放大器单元耦合到位线，以在预定义的位线信号发展间隔期间感测其上的显影信号。 放大器在随后的设置间隔期间设置为两个逻辑状态之一。 采用电隔离器在设定间隔期间将位线与读出放大器去耦，使位线上的信号变化不影响放大器。 每个位线还具有相关联的参考电压线，并且电隔离器在放大器的设置周期期间将位线和相关联的参考电压线与读出放大器隔离。

公开(公告)号：US08812879B2

公开(公告)日：2014-08-19

申请号：US12650516

申请日：2009-12-30

Applicant: Huajun Wen ,  Joshua D. Friedrich ,  Norman K. James ,  Seongwon Kim ,  John R. Ripley ,  Edmund J. Sprogis

Inventor： Huajun Wen ,  Joshua D. Friedrich ,  Norman K. James ,  Seongwon Kim ,  John R. Ripley ,  Edmund J. Sprogis

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/3203 ,  G05F1/56 ,  G06F1/26 ,  G06F1/3287 ,  Y02D10/171

Abstract: A voltage regulator module (VRM) includes a first interface configured to couple to a first substrate interface at a first voltage. The VRM also includes a second interface configured to couple to a first processor interface at a second voltage. A first regulator module couples to the first interface and to the second interface. The first regulator module is configured to receive power at the first interface, to convert power to the second voltage, and to deliver power to the first processor interface at the second voltage. A method for providing power to a processor includes receiving power from a first substrate interface at a first voltage. The received power is regulated to generate power at a second voltage. The regulated power is provided to a processor at a first processor interface coupled to the processor. The processor interface delivers power to a logic group of a plurality of logic groups of the processor.

Abstract translation: 电压调节器模块（VRM）包括被配置为以第一电压耦合到第一衬底接口的第一接口。 VRM还包括被配置为以第二电压耦合到第一处理器接口的第二接口。 第一调节器模块耦合到第一接口和第二接口。 第一调节器模块被配置为在第一接口处接收电力，以将功率转换为第二电压，并且以第二电压将功率输送到第一处理器接口。 向处理器提供电力的方法包括以第一电压从第一基板接口接收功率。 接收的功率被调节以在第二电压下产生功率。 将调节的功率提供给耦合到处理器的第一处理器接口处的处理器。 处理器接口向处理器的多个逻辑组的逻辑组递送电力。

公开(公告)号：US08564113B2

公开(公告)日：2013-10-22

申请号：US13444193

申请日：2012-04-11

Applicant: Paul S. Andry ,  Edward C. Cooney, III ,  Edmund J. Sprogis ,  Anthony K. Stamper ,  Cornelia K. Tsang

Inventor： Paul S. Andry ,  Edward C. Cooney, III ,  Edmund J. Sprogis ,  Anthony K. Stamper ,  Cornelia K. Tsang

IPC: H01L23/488

CPC classification number: H01L24/10 ,  H01L23/5384 ,  H01L24/13 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01327 ,  H01L2924/04953 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/049

Abstract: A back of a dielectric transparent handle substrate is coated with a blanket conductive film or a mesh of conductive wires. A semiconductor substrate is attached to the transparent handle substrate employing an adhesive layer. The semiconductor substrate is thinned in the bonded structure to form a stack of the transparent handle substrate and the semiconductor interposer. The thinned bonded structure may be loaded into a processing chamber and electrostatically chucked employing the blanket conductive film or the mesh of conductive wires. The semiconductor interposer may be bonded to a semiconductor chip or a packaging substrate employing C4 bonding or intermetallic alloy bonding. Illumination of ultraviolet radiation to the adhesive layer is enabled, for example, by removal of the blanket conductive film or through the mesh so that the transparent handle substrate may be detached. The semiconductor interposer may then be bonded to a packaging substrate or a semiconductor chip.

Abstract translation: 电介质透明手柄基板的背面涂覆有橡皮布导电膜或导电丝网。 使用粘合剂层将半导体衬底附接到透明手柄衬底。 半导体衬底在接合结构中变薄以形成透明手柄衬底和半导体插入器的堆叠。 减薄的粘合结构可以被加载到处理室中并且使用橡皮布导电膜或导线的网状物静电夹持。 半导体插入件可以结合到采用C4键合或金属间化合物键合的半导体芯片或封装衬底。 照射紫外线到粘合剂层是可以实现的，例如，通过去除橡皮布传导膜或通过网格，使透明手柄基板可以分离。 然后可以将半导体中介层结合到封装衬底或半导体芯片。

公开(公告)号：US08558345B2

公开(公告)日：2013-10-15

申请号：US12614883

申请日：2009-11-09

Applicant: Tae Hong Kim ,  Edmund J. Sprogis ,  Michael F. McAllister ,  Michael J. Shapiro

Inventor： Tae Hong Kim ,  Edmund J. Sprogis ,  Michael F. McAllister ,  Michael J. Shapiro

IPC: H01L27/108 ,  H01L29/94 ,  H01L23/04 ,  H01L21/02

CPC classification number: H01L28/40 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/642 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/13025 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A capacitor in a semiconductor substrate employs a conductive through-substrate via (TSV) as an inner electrode and a columnar doped semiconductor region as an outer electrode. The capacitor provides a large decoupling capacitance in a small area, and does not impact circuit density or a Si3D structural design. Additional conductive TSV's can be provided in the semiconductor substrate to provide electrical connection for power supplies and signal transmission therethrough. The capacitor has a lower inductance than a conventional array of capacitors having comparable capacitance, thereby enabling reduction of high frequency noise in the power supply system of stacked semiconductor chips.

Abstract translation: 半导体衬底中的电容器采用导电贯穿衬底通孔（TSV）作为内部电极和柱状掺杂半导体区域作为外部电极。 电容器在小面积上提供大的去耦电容，并且不影响电路密度或Si3D结构设计。 可以在半导体衬底中提供附加的导电TSV，以提供用于电源和通过其的信号传输的电连接。 电容器具有比具有相当电容的传统电容器阵列更低的电感，从而能够降低层叠半导体芯片的电源系统中的高频噪声。

公开(公告)号：US20130105981A1

公开(公告)日：2013-05-02

申请号：US13285443

申请日：2011-10-31

Applicant: Edward C. Cooney, III ,  James S. Dunn ,  Dale W. Martin ,  Charles F. Musante ,  BethAnn Rainey ,  Leathen Shi ,  Edmund J. Sprogis ,  Cornelia K. Tsang

Inventor： Edward C. Cooney, III ,  James S. Dunn ,  Dale W. Martin ,  Charles F. Musante ,  BethAnn Rainey ,  Leathen Shi ,  Edmund J. Sprogis ,  Cornelia K. Tsang

IPC: H01L23/48 ,  H01L21/58

CPC classification number: H01L23/4825 ,  H01L21/6835 ,  H01L21/76819 ,  H01L22/32 ,  H01L22/34 ,  H01L23/5223 ,  H01L23/5283 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/80 ,  H01L24/81 ,  H01L29/1054 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05687 ,  H01L2224/06181 ,  H01L2224/08225 ,  H01L2224/131 ,  H01L2224/73251 ,  H01L2224/80011 ,  H01L2224/80013 ,  H01L2224/80075 ,  H01L2224/80203 ,  H01L2224/804 ,  H01L2224/80487 ,  H01L2224/80896 ,  H01L2224/80907 ,  H01L2224/80948 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/15788 ,  H01L2924/014 ,  H01L2224/08 ,  H01L2224/16 ,  H01L2924/05432 ,  H01L2924/053 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/04941 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures of a product chip are formed using a first surface of a device substrate. A wiring layer of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate. The temporary handle wafer is then removed from the assembly.

Abstract translation: 用于粘结衬底表面，键合衬底组件和用于键合衬底组件的设计结构的方法。 使用器件基板的第一表面形成产品芯片的器件结构。 在产品芯片上形成用于器件结构的互连结构的布线层。 布线层被平坦化。 临时处理晶片可移除地结合到平坦化的布线层。 响应于将临时手柄晶片可移除地结合到平坦化的第一布线层，与第一表面相对的器件基板的第二表面被结合到最终的手柄基板。 然后将临时手柄晶片从组件中取出。

公开(公告)号：US08242591B2

公开(公告)日：2012-08-14

申请号：US12540510

申请日：2009-08-13

Applicant: Paul S. Andry ,  Edward C. Cooney, III ,  Edmund J. Sprogis ,  Anthony K. Stamper ,  Cornelia K. Tsang

Inventor： Paul S. Andry ,  Edward C. Cooney, III ,  Edmund J. Sprogis ,  Anthony K. Stamper ,  Cornelia K. Tsang

IPC: H01L23/488

CPC classification number: H01L24/10 ,  H01L23/5384 ,  H01L24/13 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01327 ,  H01L2924/04953 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/049

Abstract: A back of a dielectric transparent handle substrate is coated with a blanket conductive film or a mesh of conductive wires. A semiconductor substrate is attached to the transparent handle substrate employing an adhesive layer. The semiconductor substrate is thinned in the bonded structure to form a stack of the transparent handle substrate and the semiconductor interposer. The thinned bonded structure may be loaded into a processing chamber and electrostatically chucked employing the blanket conductive film or the mesh of conductive wires. The semiconductor interposer may be bonded to a semiconductor chip or a packaging substrate employing C4 bonding or intermetallic alloy bonding. Illumination of ultraviolet radiation to the adhesive layer is enabled, for example, by removal of the blanket conductive film or through the mesh so that the transparent handle substrate may be detached. The semiconductor interposer may then be bonded to a packaging substrate or a semiconductor chip.

Abstract translation: 电介质透明手柄基板的背面涂覆有橡皮布导电膜或导电丝网。 使用粘合剂层将半导体衬底附接到透明手柄衬底。 半导体衬底在接合结构中变薄以形成透明手柄衬底和半导体插入器的堆叠。 减薄的粘合结构可以被加载到处理室中并且使用橡皮布导电膜或导线的网状物静电夹持。 半导体插入件可以结合到采用C4键合或金属间化合物键合的半导体芯片或封装衬底。 照射紫外线到粘合剂层是可以实现的，例如，通过去除橡皮布传导膜或通过网格，使透明手柄基板可以分离。 然后可以将半导体中介层结合到封装衬底或半导体芯片。

公开(公告)号：US08187923B2

公开(公告)日：2012-05-29

申请号：US12167745

申请日：2008-07-03

Applicant: Paul Stephen Andry ,  Leena Paivikki Buchwalter ,  Matthew J. Farinelli ,  Sherif A. Goma ,  Raymond R. Horton ,  Edmund J. Sprogis

Inventor： Paul Stephen Andry ,  Leena Paivikki Buchwalter ,  Matthew J. Farinelli ,  Sherif A. Goma ,  Raymond R. Horton ,  Edmund J. Sprogis

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L21/67092 ,  H01L21/67132 ,  H01L21/6835 ,  H01L21/6836 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68354 ,  H01L2224/11003 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/10253 ,  Y10S414/139 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A laser release and glass chip removal process for a integrated circuit module avoiding carrier edge cracking is provided.

Abstract translation: 提供了用于避免载波边缘破裂的集成电路模块的激光释放和玻璃切屑去除工艺。

公开(公告)号：US08039356B2

公开(公告)日：2011-10-18

申请号：US12690299

申请日：2010-01-20

Applicant: Russell T. Herrin ,  Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

Inventor： Russell T. Herrin ,  Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

IPC: H01L21/76

CPC classification number: H01L21/76898 ,  G03F9/7076 ,  G03F9/708 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing an integrated circuit structure forms a first opening in a substrate and lines the first opening with a protective liner. The method deposits a material into the first opening and forms a protective material over the substrate. The protective material includes a process control mark and includes a second opening above, and aligned with, the first opening. The method removes the material from the first opening through the second opening in the protective material. The process control mark comprises a recess within the protective material that extends only partially through the protective material, such that portions of the substrate below the process control mark are not affected by the process of removing the material.

Abstract translation: 一种制造集成电路结构的方法在衬底中形成第一开口并且用保护性衬垫对第一开口进行排列。 该方法将材料沉积到第一开口中并在基底上形成保护材料。 保护材料包括工艺控制标记，并且包括在第一开口上方并对准第二开口的第二开口。 该方法通过保护材料中的第二开口从第一开口移除材料。 过程控制标记包括在保护材料内的仅部分延伸穿过保护材料的凹槽，使得在过程控制标记之下的基底的部分不受去除材料的过程的影响。

公开(公告)号：US20110108948A1

公开(公告)日：2011-05-12

申请号：US12614883

申请日：2009-11-09

Applicant: Tae Hong Kim ,  Edmund J. Sprogis ,  Michael F. McAllister ,  Michael J. Shapiro

Inventor： Tae Hong Kim ,  Edmund J. Sprogis ,  Michael F. McAllister ,  Michael J. Shapiro

IPC: H01L29/92 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L28/40 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/642 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/13025 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A capacitor in a semiconductor substrate employs a conductive through-substrate via (TSV) as an inner electrode and a columnar doped semiconductor region as an outer electrode. The capacitor provides a large decoupling capacitance in a small area, and does not impact circuit density or a Si3D structural design. Additional conductive TSV's can be provided in the semiconductor substrate to provide electrical connection for power supplies and signal transmission therethrough. The capacitor has a lower inductance than a conventional array of capacitors having comparable capacitance, thereby enabling reduction of high frequency noise in the power supply system of stacked semiconductor chips.

Abstract translation: 半导体衬底中的电容器采用导电贯穿衬底通孔（TSV）作为内部电极和柱状掺杂半导体区域作为外部电极。 电容器在小面积上提供大的去耦电容，并且不影响电路密度或Si3D结构设计。 可以在半导体衬底中提供附加的导电TSV，以提供用于电源和通过其的信号传输的电连接。 电容器具有比具有相当电容的传统电容器阵列更低的电感，从而能够降低层叠半导体芯片的电源系统中的高频噪声。