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    APPARATUS, SYSTEM, AND METHOD OF A DIGITALLY-CONTROLLED FREQUENCY MULTIPLIER
    22.
    发明申请
    APPARATUS, SYSTEM, AND METHOD OF A DIGITALLY-CONTROLLED FREQUENCY MULTIPLIER 有权

    公开(公告)号：US20220329248A1

    公开(公告)日：2022-10-13

    申请号：US17842585

    申请日：2022-06-16

    Applicant: Intel Corporation

    Inventor： Ali Azam ,  Ashoke Ravi ,  Ofir Degani

    IPC: H03L7/197 ,  H03L7/081 ,  H03L7/091 ,  H03L7/093

    Abstract: For example, an apparatus may include a digitally-controlled frequency multiplier, which may be controllable according to a digital control input, to generate an output frequency signal having an output frequency, for example, by multiplying an input frequency of an input frequency signal. For example, the digitally-controlled frequency multiplier may include a phase generator configured to generate a plurality of phase-shifted signal groups corresponding to a respective plurality of first phase-shifts applied to the input frequency signal, a plurality of digital clock multipliers controllable according to the digital control input to generate a respective plurality of frequency-multiplied signals based on the plurality of phase-shifted signal groups, and a combiner to generate the output frequency signal based on a combination of the plurality of frequency-multiplied signals.

    Systems and Methods for Frequency Domain Calibration and Characterization
    26.
    发明申请
    Systems and Methods for Frequency Domain Calibration and Characterization 审中-公开
    频域校准和表征的系统和方法

    公开(公告)号：US20170070232A1

    公开(公告)日：2017-03-09

    申请号：US15354066

    申请日：2016-11-17

    Applicant: Intel Corporation

    Inventor： Cho-Ying Lu ,  William Yee Li ,  Khoa Minh Nguyen ,  Ashoke Ravi ,  Maneesha Yellepeddi ,  Binta M. Patel

    IPC: H03L7/099 ,  H03L7/091 ,  H03L1/00

    CPC classification number: H03L7/085 ,  H03L1/00 ,  H03L7/08 ,  H03L7/091 ,  H03L7/0991 ,  H03L7/0992 ,  H03L2207/50

    Abstract: A system for assigning a characterization and calibrating a parameter is disclosed. The system includes a frequency measurement circuit and a finite state machine. The frequency measurement circuit is configured to measure frequencies of an oscillatory signal and to generate a measurement signal including measured frequencies. The finite state machine is configured to control measurements by the frequency measurement circuit, to assign a characterization to a parameter based on the measurement signal, and to generate a calibration signal based on the characterized parameter.

    Abstract translation: 公开了一种用于分配表征和校准参数的系统。 该系统包括频率测量电路和有限状态机。 频率测量电路被配置为测量振荡信号的频率并产生包括测量频率的测量信号。 有限状态机被配置为通过频率测量电路来控制测量，基于测量信号为参数分配表征，并且基于所表征的参数来产生校准信号。

    Methods and systems to compensate for non-linearity of a stochastic system
    28.
    发明授权
    Methods and systems to compensate for non-linearity of a stochastic system 有权
    补偿随机系统非线性的方法和系统

    公开(公告)号：US09361064B2

    公开(公告)日：2016-06-07

    申请号：US14022683

    申请日：2013-09-10

    Applicant: INTEL CORPORATION

    Inventor： Ofir Degani ,  Ashoke Ravi ,  Hasnain Lakdawala

    IPC: H03M1/10 ,  G06F5/00 ,  G04F10/00 ,  H03L7/085

    CPC classification number: G06F5/00 ,  G04F10/005 ,  H03L7/085 ,  H03L2207/50 ,  H03M1/1014 ,  H03M1/1033

    Abstract: Determination of digital compensation to compensate for non-linearity of stochastic system configured to sample a phase difference, based on statistical analysis of calibration data generated by the stochastic system in response to a linear phase ramp. The stochastic system may include a set of stochastic sampler circuits to sample a phase difference at periodic events, and calibration data may include a digital value of set of stochastic samples for each of multiple events. The calibration data may include sequences of the digital values in which the digital values increment over a range of the stochastic system (i.e., between saturation states of the stochastic system). Statistical analysis may include histogram analysis to estimate the probability distribution of the calibration data. The stochastic system may be configured as part of a time-to-digital converter, which may be configured within a feedback loop of a digitally controllable phase lock loop.

    Abstract translation: 基于随机系统响应于线性相位斜坡生成的校准数据的统计分析，确定数字补偿以补偿配置为采样相位差的随机系统的非线性。 随机系统可以包括一组随机采样器电路，以在周期性事件中采样相位差，并且校准数据可以包括多个事件中的每一个的随机样本集合的数字值。 校准数据可以包括数字值的序列，其中数字值在随机系统的范围（即，随机系统的饱和状态之间）增加。 统计分析可以包括直方图分析来估计校准数据的概率分布。 随机系统可以被配置为时间 - 数字转换器的一部分，其可以配置在数字可控锁相环的反馈回路内。

    Segmented digital-to-time converter calibration
    29.
    发明授权
    Segmented digital-to-time converter calibration 有权
    分段数字到时间转换器校准

    公开(公告)号：US09209958B1

    公开(公告)日：2015-12-08

    申请号：US14318799

    申请日：2014-06-30

    Applicant: Intel Corporation

    Inventor： Georgios Palaskas ,  Paolo Madoglio ,  Stefano Pellerano ,  Ashoke Ravi ,  Kailash Chandrashekar

    IPC: H03K7/06 ,  H03C3/00 ,  H04L27/12 ,  H04L7/00 ,  H04B17/21

    CPC classification number: H04L7/0004 ,  G04F10/005 ,  H04B17/14 ,  H04B17/21 ,  H04L7/0087

    Abstract: This application discusses, among other things, calibration systems for ameliorating nonlinearity of a digital-to-time converter (DTC). In an example, a calibration system can include a calibration path configured to represent a segment of the DTC, a time-to-digital circuit configured to receive an output of the calibration path and the processed frequency information and to provide timing error information of the segment, and a calibration engine configured to receive controller modulation information from a main controller, to provide calibration modulation information to the DTC, to receive the timing error information, and to provide compensation information to a correction circuit coupled to the DTC using the timing error information.

    Abstract translation: 该应用程序除其他外还讨论了用于改善数字 - 时间转换器（DTC）的非线性的校准系统。 在一个示例中，校准系统可以包括被配置为表示DTC的段的校准路径，配置成接收校准路径的输出和经处理的频率信息的时间到数字电路，并且提供定时误差信息 并且校准引擎被配置为从主控制器接收控制器调制信息，以向DTC提供校准调制信息以接收定时误差信息，并且使用定时误差向耦合到DTC的校正电路提供补偿信息 信息。

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