公开(公告)号：US06458623B1

公开(公告)日：2002-10-01

申请号：US09765030

申请日：2001-01-17

Applicant: Lewis S. Goldmann ,  Mario J. Interrante ,  Raymond A. Jackson ,  Amy B. Ostrander ,  Charles H. Perry ,  Brenda L. Peterson

Inventor： Lewis S. Goldmann ,  Mario J. Interrante ,  Raymond A. Jackson ,  Amy B. Ostrander ,  Charles H. Perry ,  Brenda L. Peterson

IPC: H01L2144

CPC classification number: H01L24/83 ,  H01L23/49827 ,  H01L24/29 ,  H01L24/81 ,  H01L2224/13111 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/81801 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/30107 ,  H05K3/321 ,  H05K3/3436 ,  H05K2201/09472 ,  H05K2201/10992 ,  H05K2203/041 ,  H05K2203/0415 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/01083 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929

Abstract: A method and apparatus is provided for forming an electronic assembly whereby an insulating polymer matrix having a plurality of conductor holes is attached to a first substrate wherein the conductor holes align with a corresponding contact array on the first substrate. Subsequently, a flexible, electrically conductive adhesive is provided within the plurality of conductor holes and a solid conductive material, preferably having a high melting temperature, is attached to at least one end thereof. The insulating polymer matrix with the electrically conductive adhesive and the solid conductive material is then cured at a temperature sufficient to completely cure the matrix to completely surround the electrically conductive adhesive, as well as permanently attaching the matrix and conductive adhesive to the first substrate and permanently attaching the solid conductive material to the conductive adhesive. A second substrate may then be attached to the conductive matrix structure secured to the first substrate by providing a low melting temperature attachment means to the solid conductive material attached to the matrix and subsequently reflowing the assembly to form an electronic assembly adapted with the capability of reworkability.

Abstract translation: 提供了一种用于形成电子组件的方法和装置，由此具有多个导体孔的绝缘聚合物基体附接到第一基底，其中导体孔与第一基底上的对应的接触阵列对准。 随后，在多个导体孔内提供柔性的导电粘合剂，并且其至少一端连接有优选具有高熔融温度的固体导电材料。 然后将具有导电粘合剂和固体导电材料的绝缘聚合物基质在足以完全固化基质以完全包围导电粘合剂的温度下固化，以及将基质和导电粘合剂永久地附着到第一基材上并永久地 将固体导电材料附着到导电粘合剂上。 然后可以通过向连接到基质的固体导电材料提供低熔点温度的附着装置，随后回流组件以形成适于具有再加工性能的电子组件，然后将第二衬底附接到固定到第一衬底的导电矩阵结构 。

公开(公告)号：US06360938B1

公开(公告)日：2002-03-26

申请号：US09794597

申请日：2001-02-27

Applicant: Stephen A. DeLaurentis ,  Mario J. Interrante ,  Raymond A. Jackson ,  John U. Knickerbocker ,  Sudipta K. Ray ,  Kathleen A. Stalter

Inventor： Stephen A. DeLaurentis ,  Mario J. Interrante ,  Raymond A. Jackson ,  John U. Knickerbocker ,  Sudipta K. Ray ,  Kathleen A. Stalter

IPC: B23K1018

Abstract: A process and apparatus for removing flip chips with C4 joints mounted on a multi-chip module by applying a tensile force to one or more removal member bonded to the back of one or more flip chips during heating of the module to a temperature sufficient to cause the C4 joints to become molten. The tensile force can either be a compressed spring, or a bi-metallic member which is flat at room temperature and becomes curved when heated to such temperature, or a memory alloy whose original shape is curved and which is bent flat at room temperature but returns to its original curved shape when heated to such temperature. An adhesive is used to bond the removal member to the chip to be removed and is a low temperature, fast curing adhesive with high temperature tolerance after curing.

公开(公告)号：US06287126B1

公开(公告)日：2001-09-11

申请号：US09344887

申请日：1999-06-25

Applicant: Michael Berger ,  Lewis S. Goldmann ,  Harvey C. Hamel ,  Mario J. Interrante ,  Marlene W. Moyer ,  Thomas P. Moyer ,  Karl J. Puttlitz, Sr.

Inventor： Michael Berger ,  Lewis S. Goldmann ,  Harvey C. Hamel ,  Mario J. Interrante ,  Marlene W. Moyer ,  Thomas P. Moyer ,  Karl J. Puttlitz, Sr.

IPC: H01R1200

CPC classification number: H01R4/64

Abstract: An electrical connector arrangement for connecting electronic devices to one another. The connector arrangement uses tensile members and compression members, at least the tensile members of which act to provide both an electrical connection between electronic devices and force over a range of distances to hold the devices together. The tensile members provides tensile force acting to hold the electronic devices together while the compression members provide an opposing compressive force over a range of distances which balances the tensile force to thereby form a cellforce connector used to connect an array of electrical contact points on one electronic device to a corresponding array of electrical contact points on another electronic device.

Abstract translation: 一种用于将电子设备彼此连接的电连接器装置。 连接器装置使用拉伸构件和压缩构件，其至少其拉伸构件用于提供电子装置之间的电连接并在一定距离范围内施力以将装置保持在一起。 拉伸构件提供作用以将电子装置保持在一起的张力，同时压缩构件在一定距离范围内提供相反的压缩力，其平衡拉伸力从而形成用于连接一个电子装置上的电接触点阵列的电池单元连接器 设备到另一电子设备上的对应的电接触点阵列。

公开(公告)号：US06283359B1

公开(公告)日：2001-09-04

申请号：US09644486

申请日：2000-08-23

Applicant: Peter J. Brofman ,  Mark G. Courtney ,  Shaji Farooq ,  Mario J. Interrante ,  Raymond A. Jackson ,  Gregory B. Martin ,  Sudipta K. Ray ,  William E. Sablinski ,  Kathleen A. Stalter

Inventor： Peter J. Brofman ,  Mark G. Courtney ,  Shaji Farooq ,  Mario J. Interrante ,  Raymond A. Jackson ,  Gregory B. Martin ,  Sudipta K. Ray ,  William E. Sablinski ,  Kathleen A. Stalter

IPC: B23K3102

CPC classification number: H01L24/12 ,  B23K35/0222 ,  B23K35/0244 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/1184 ,  H01L2224/13099 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H05K3/3436 ,  H05K2201/10992 ,  H05K2203/041 ,  H05K2203/0415 ,  H05K2203/0435 ,  Y02P70/613 ,  Y10T428/12687 ,  Y10T428/2991 ,  H01L2224/29099 ,  H01L2924/00

Abstract: This invention relates to a solder structure which provides enhanced fatigue life properties when used to bond substrates particularly at the second level such as BGA and CGA interconnections. The solder structure is preferably a sphere or column and has a metal layer wettable by solder and the structure is used to make solder connections in electronic components such as joining an electronic module such as a chip connected to a MLC which module is connected to a circuit board. The solder structure preferably has an overcoat of solder on the metal layer to provide a passivation coating to the metal layer to keep it clean from oxidation and corrosion and also provide a wettable surface for attachment of the solder structure to solder on the pads of the substrate being bonded.

Abstract translation: 本发明涉及一种焊料结构，当用于特别是在第二层（例如BGA和CGA互连）的基材上时，其提供增强的疲劳寿命特性。 焊料结构优选是球形或柱状，并且具有可被焊料润湿的金属层，并且该结构用于在电子部件中形成焊接连接​​，例如连接诸如连接到MLC的芯片的电子模块，该模块连接到电路 板。 焊料结构优选地在金属层上具有焊料的外涂层，以向金属层提供钝化涂层以保持其免于氧化和腐蚀，并且还提供用于将焊料结构附着到衬底的焊盘上的焊料的可润湿表面 被绑定。

公开(公告)号：US5193732A

公开(公告)日：1993-03-16

申请号：US771706

申请日：1991-10-04

Applicant: Mario J. Interrante ,  Michael Berger ,  Edward F. Handford ,  Eugene Tas

Inventor： Mario J. Interrante ,  Michael Berger ,  Edward F. Handford ,  Eugene Tas

IPC: B23K20/10 ,  H01L21/607 ,  H05K3/22 ,  H05K3/32 ,  H05K3/34 ,  H05K3/40

CPC classification number: H01L24/85 ,  B23K20/10 ,  H01L24/48 ,  H01L24/78 ,  H05K3/225 ,  H01L2224/45109 ,  H01L2224/45113 ,  H01L2224/45116 ,  H01L2224/4512 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45164 ,  H01L2224/45169 ,  H01L2224/45171 ,  H01L2224/4518 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/78313 ,  H01L2224/8501 ,  H01L2224/85191 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/8592 ,  H01L24/45 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/19041 ,  H05K2201/10287 ,  H05K2203/0285 ,  H05K2203/049 ,  H05K2203/173 ,  H05K3/328 ,  H05K3/3457

Abstract: The present invention relates generally to apparatus and methods for making simultaneous electrical connections, and more particularly to making these electrical connections simultaneously using a new bond tip configuration. Various methods and processes are being disclosed to simultaneously make electrical connections between electrical conductor lines or pads. The electrical connection is made by placing an electrically conductive wire across a pair of electrical lines or pads that have to be electrically connected and then by using a special tip, both ends of the electrically conductive wire are simultaneously secured to the two electrically conductive lines or pads.

公开(公告)号：US20130015579A1

公开(公告)日：2013-01-17

申请号：US13615804

申请日：2012-09-14

Applicant: Luc Guerin ,  Mario J. Interrante ,  Michael J. Shapiro ,  Thuy Tran-Quinn ,  Van T. Truong

Inventor： Luc Guerin ,  Mario J. Interrante ,  Michael J. Shapiro ,  Thuy Tran-Quinn ,  Van T. Truong

IPC: H01L23/488

CPC classification number: H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/03462 ,  H01L2224/03618 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/0566 ,  H01L2224/05681 ,  H01L2224/10126 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/01026 ,  H01L2224/05552

Abstract: A solder ball contact and a method of making a solder ball contact includes: a first insulating layer with a via formed on an integrated circuit (IC) chip and a metal pad; an under bump metallurgy (UBM) structure disposed within the via and on a portion of the first insulating layer, surrounding the via; a second insulating layer formed on an upper surface of an outer portion of the UBM structure that is centered on the via; and a solder ball that fills the via and is disposed above an upper surface of an inner portion of the UBM structure that contacts the via, in which the UBM structure that underlies the solder ball is of a greater diameter than the solder ball.

Abstract translation: 焊球接触和制造焊球接触的方法包括：在集成电路（IC）芯片和金属焊盘上形成有通孔的第一绝缘层; 设置在所述通孔内和所述第一绝缘层的围绕所述通孔的部分上的凸块下冶金（UBM）结构; 第二绝缘层，形成在所述UBM结构的位于所述通孔的中心的外部的上表面上; 以及填充通孔并且设置在UBM结构的与通孔接触的内部的上表面上方的焊球，其中在焊球下面的UBM结构具有比焊球更大的直径。

公开(公告)号：US06762119B2

公开(公告)日：2004-07-13

申请号：US09885791

申请日：2001-06-20

Applicant: Sudipta K. Ray ,  Mitchell S. Cohen ,  Lester Wynn Herron ,  Mario J. Interrante ,  Thomas E. Lombardi ,  Subhash L. Shinde

Inventor： Sudipta K. Ray ,  Mitchell S. Cohen ,  Lester Wynn Herron ,  Mario J. Interrante ,  Thomas E. Lombardi ,  Subhash L. Shinde

IPC: H01L2144

CPC classification number: H01S5/02272 ,  G02B6/4238 ,  H01L24/45 ,  H01L2224/45144 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01S5/02236 ,  H01S5/02268 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A process and structure for forming an optical subassembly in an integrated circuit, comprising: defining electrically conducting lines and bonding pads in a metallization layer on a substrate; depositing a passivation layer over the metallization layer; etching the passivation layer to remove the passivation layer from each of the bonding pads and a portion of the metallization layer associated with each of the bonding pads; diffusing Cr from the lines proximate said bonding pads to prevent solder wetting down lines; bonding an optical device to one of the bonding pads; and attaching the substrate to a carrier utilizing solder bond attachment.

Abstract translation: 一种用于在集成电路中形成光学子组件的工艺和结构，包括：在衬底上的金属化层中限定导电线和焊盘; 在所述金属化层上沉积钝化层; 蚀刻钝化层以从每个接合焊盘和与每个焊盘相关联的金属化层的一部分去除钝化层; 从靠近所述接合焊盘的线扩散Cr，以防止焊料向下润湿; 将光学器件接合到所述接合焊盘之一; 以及使用焊料粘合附着将衬底附接到载体上。

公开(公告)号：US06740959B2

公开(公告)日：2004-05-25

申请号：US09921062

申请日：2001-08-01

Applicant: David James Alcoe ,  Jeffrey Thomas Coffin ,  Michael Anthony Gaynes ,  Harvey Charles Hamel ,  Mario J. Interrante ,  Brenda Lee Peterson ,  Megan J. Shannon ,  William Edward Sablinski ,  Christopher Todd Spring ,  Randall Joseph Stutzman ,  Renee L. Weisman ,  Jeffrey Allen Zitz

Inventor： David James Alcoe ,  Jeffrey Thomas Coffin ,  Michael Anthony Gaynes ,  Harvey Charles Hamel ,  Mario J. Interrante ,  Brenda Lee Peterson ,  Megan J. Shannon ,  William Edward Sablinski ,  Christopher Todd Spring ,  Randall Joseph Stutzman ,  Renee L. Weisman ,  Jeffrey Allen Zitz

IPC: H01L23552

CPC classification number: H01L23/552 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01087 ,  H01L2924/12044 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3025 ,  H01L2924/00

Abstract: Electronic packages incorporating EMI shielding, and particularly semiconductor devices which incorporate semiconductor chip-carrier structures having grounded bands embedded therein which are adapted to reduce outgoing and incident EMI emissions for high-speed switching electronic packages.

Abstract translation: 包括EMI屏蔽的电子封装，特别是包含嵌入其中具有接地带的半导体芯片 - 载体结构的半导体器件，其适于减少高速开关电子封装的输出和入射EMI发射。

公开(公告)号：US06429388B1

公开(公告)日：2002-08-06

申请号：US09564110

申请日：2000-05-03

Applicant: Mario J. Interrante ,  Brenda Peterson ,  Sudipta K. Ray ,  William E. Sablinski ,  Amit K. Sarkhel

Inventor： Mario J. Interrante ,  Brenda Peterson ,  Sudipta K. Ray ,  William E. Sablinski ,  Amit K. Sarkhel

IPC: H01R909

CPC classification number: B23K35/262 ,  H01L23/488 ,  H01L23/49811 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13109 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01322 ,  H05K3/3426 ,  H05K3/3436 ,  H05K3/3463 ,  H05K3/4015 ,  H05K2201/10242 ,  H05K2203/047 ,  Y02P70/613 ,  H01L2224/29099 ,  H01L2224/05599

Abstract: The present invention relates generally to a new semiconductor chip carrier connections, where the chip carrier and the second level assembly are made by a surface mount technology. More particularly, the invention encompasses surface mount technologies, such as, Ball Grid Array (BGA), Column Grid Array (CGA), to name a few, where the surface mount technology comprises essentially of a non-solder metallic connection, such as, a copper connection. The present invention is also related to Column Grid Array structures and process thereof.

Abstract translation: 本发明一般涉及新的半导体芯片载体连接，其中芯片载体和第二级组件是通过表面贴装技术制成的。 更具体地，本发明包括表面贴装技术，例如球栅阵列（BGA），柱栅阵列（CGA），其中表面贴装技术基本上由非焊料金属连接构成，例如， 铜连接。 本发明还涉及列格阵列结构及其工艺。

公开(公告)号：US06235996B1

公开(公告)日：2001-05-22

申请号：US09014804

申请日：1998-01-28

Applicant: Shaji Farooq ,  Mario J. Interrante ,  Sudipta K. Ray ,  William E. Sablinski

Inventor： Shaji Farooq ,  Mario J. Interrante ,  Sudipta K. Ray ,  William E. Sablinski

IPC: H01L2348

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/19105 ,  H05K3/3436 ,  H05K3/3463 ,  H05K3/3484 ,  H05K2201/0215 ,  H05K2201/0272 ,  H05K2201/094 ,  H05K2201/10992 ,  H05K2203/041 ,  H05K2203/0415 ,  Y02P70/613 ,  Y10T29/49126 ,  H01L2924/00

Abstract: An interconnection structure and methods for making and detaching the same are presented for column and ball grid array (CGA and BGA) structures by using a transient solder paste on the electronic module side of the interconnection that includes fine metal powder additives to increase the melting point of the solder bond. The metal powder additives change the composition of the solder bond such that the transient melting solder composition does not completely melt at temperatures below +230° C. and detach from the electronic module during subsequent reflows. A Pb—Sn eutectic with a lower melting point is used on the opposite end of the interconnection structure. In the first method a transient melting solder paste is applied to the I/O pad of an electronic module by a screening mask. Interconnect structures are then bonded to the I/O pad. In a second method, solder preforms in a composition of the transient melting solder paste are wetted onto electronic module I/O pads and interconnect columns or balls are then bonded. Detachment of an electronic module from a circuit card can then be performed by heating the circuit card assembly to a temperature above the eutectic solder melting point, but below the transient solder joint melting point.

Abstract translation: 通过使用包括细金属粉末添加剂的电子模块侧的瞬态焊膏来提供柱和球栅阵列（CGA和BGA）结构的互连结构及其分离方法，以增加熔点 的焊点。 金属粉末添加剂改变焊料接合的组成，使得瞬态熔融焊料组合物在低于+ 230℃的温度下不会完全熔化，并且在随后的回流期间与电子模块分离。 在互连结构的另一端使用具有较低熔点的Pb-Sn共晶体。 在第一种方法中，通过屏蔽掩模将瞬态熔融焊膏施加到电子模块的I / O焊盘。 然后将互连结构结合到I / O焊盘。 在第二种方法中，将瞬态熔融焊膏的组合物中的焊料预成型件润湿到电子模块I / O焊盘上，然后将互连柱或球接合。 然后可以通过将电路卡组件加热到高于共熔焊料熔点但低于瞬态焊点熔点的温度来执行从电路卡分离电子模块。