公开(公告)号：US08426981B2

公开(公告)日：2013-04-23

申请号：US13240048

申请日：2011-09-22

申请人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima

发明人： Yoshitaka Sasaki ,  Hiroyuki Ito ,  Atsushi Iijima

IPC分类号： H01L23/48 ,  H01L23/02 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/96 ,  H01L21/6835 ,  H01L24/06 ,  H01L24/24 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03011 ,  H01L2224/0346 ,  H01L2224/03618 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05644 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/83005 ,  H01L2224/94 ,  H01L2225/06551 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/1064 ,  H01L2924/07802 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/0105

摘要： A composite layered chip package includes first and second subpackages that are stacked. Each subpackage includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface; first terminals disposed on the top surface of the main part; and second terminals disposed on the bottom surface of the main part. The first and second terminals are electrically connected to the wiring. The first and second subpackages are arranged in a specific relative positional relationship, different from a reference relative positional relationship, with each other.

摘要翻译： 复合分层芯片封装包括堆叠的第一和第二子封装。 每个子包包括主体和接线。 主体包括：具有顶表面和底表面的主要部分; 第一端子设置在主要部件的顶表面上; 以及设置在主要部分的底表面上的第二端子。 第一端子和第二端子电连接到布线。 第一子包和第二子包以不同于参考相对位置关系的特定相对位置关系彼此排列。

公开(公告)号：US08294254B2

公开(公告)日：2012-10-23

申请号：US13409625

申请日：2012-03-01

申请人： Tao Feng

发明人： Tao Feng

IPC分类号： H01L23/02

CPC分类号： H01L29/0657 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/29 ,  H01L24/32 ,  H01L24/94 ,  H01L2224/02371 ,  H01L2224/03011 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0362 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/06182 ,  H01L2224/08225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48666 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48766 ,  H01L2224/83805 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/157 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/01079 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2224/03 ,  H01L2224/83 ,  H01L2224/48 ,  H01L2224/05552

摘要： A semiconductor device package die and method of manufacture are disclosed. The device package die may comprise a device substrate having one or more front electrodes located on a front surface of the device substrate and electrically connected to one or more corresponding device regions formed within the device substrate proximate the front surface. A back conductive layer is formed on a back surface of the device substrate. The back conductive layer is electrically connected to a device region formed within the device substrate proximate a back surface of the device substrate. One or more conductive extensions are formed on one or more corresponding sidewalls of the device substrate in electrical contact with the back conductive layer, and extend to a portion of the front surface of the device substrate. A support substrate is bonded to the back surface of the device substrate.

公开(公告)号：US20240250047A1

公开(公告)日：2024-07-25

申请号：US18598167

申请日：2024-03-07

申请人： NANYA TECHNOLOGY CORPORATION

发明人： TENG-YEN HUANG

IPC分类号： H01L23/00 ,  H01L25/065

CPC分类号： H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L24/02 ,  H01L2224/02372 ,  H01L2224/03001 ,  H01L2224/03011 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/05018 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05193 ,  H01L2224/05546 ,  H01L2224/05559 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/05676 ,  H01L2224/0568 ,  H01L2224/05684 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06181 ,  H01L2224/06517 ,  H01L2224/08145 ,  H01L2224/08146 ,  H01L2224/80379 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/0504 ,  H01L2924/0509 ,  H01L2924/0544 ,  H01L2924/059 ,  H01L2924/30105

摘要： The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure and a first connecting structure, wherein the first connecting structure includes a first connecting insulating layer positioned on the first semiconductor structure, two first conductive layers positioned in the first connecting insulating layer, and a first porous layer positioned between the two first conductive layers. A porosity of the first porous layer is between about 25% and about 100%. The first semiconductor structure includes a plurality of first composite conductive features, wherein at least one of the plurality of first composite conductive features includes a first protection liner, a first graphene liner in the first protection liner and a first core conductor in the first graphene liner.

公开(公告)号：US11955446B2

公开(公告)日：2024-04-09

申请号：US17993235

申请日：2022-11-23

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Yu-Han Hsueh

IPC分类号： H01L23/48 ,  H01L23/00

CPC分类号： H01L24/08 ,  H01L24/03 ,  H01L24/05 ,  H01L24/09 ,  H01L24/80 ,  H01L2224/03011 ,  H01L2224/05547 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/0569 ,  H01L2224/05693 ,  H01L2224/08145 ,  H01L2224/09505 ,  H01L2224/80948

摘要： The present disclosure relates to a method for forming a semiconductor device structure. The method includes forming a first semiconductor die and forming a second semiconductor die. The first semiconductor die includes a first metal layer, a first conductive via over the first metal layer, and a first conductive polymer liner surrounding the first conductive via. The second semiconductor die includes a second metal layer, a second conductive via over the second metal layer, and a second conductive polymer liner surrounding the second conductive via. The method also includes forming a conductive structure electrically connecting the first metal layer and the second metal layer by bonding the second semiconductor die to the first semiconductor die. The conductive structure is formed by the first conductive via, the first conductive polymer liner, the second conductive via, and the second conductive polymer liner.

公开(公告)号：US20230386908A1

公开(公告)日：2023-11-30

申请号：US17819341

申请日：2022-08-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Sheng-Han Tsai ,  Yuan Sheng Chiu ,  Chou-Jui Hsu ,  Tsung-Shu Lin

IPC分类号： H01L21/768 ,  H01L23/00

CPC分类号： H01L21/76829 ,  H01L21/76807 ,  H01L24/03 ,  H01L2224/03011 ,  H01L2224/02235 ,  H01L2224/02251 ,  H01L2924/35 ,  H01L2224/06179 ,  H01L2224/06151 ,  H01L2224/06155 ,  H01L24/06

摘要： A method includes forming a plurality of dielectric layers over a semiconductor substrate, forming a plurality of metal lines and vias in the plurality of dielectric layers, forming a lower portion of an inner seal ring and a lower portion of an outer seal ring extending into the plurality of dielectric layers, depositing a first dielectric layer over the plurality of metal lines and vias, and etching the first dielectric layer to form an opening penetrating through the first dielectric layer. After the first dielectric layer is etched, a top surface of the lower portion of the inner seal ring is exposed, and an entire topmost surface of the lower portion of the outer seal ring is in contact with a bottom surface of the first dielectric layer. An upper portion of the inner seal ring is then formed to extend into the opening and to join the lower portion of the inner seal ring. A second dielectric layer is deposited to cover the upper portion of the inner seal ring.

公开(公告)号：US20190189576A1

公开(公告)日：2019-06-20

申请号：US16276533

申请日：2019-02-14

申请人： Micron Technology, Inc.

发明人： Mayukhee Das ,  Jonathan S. Hacker ,  Christopher J. Gambee ,  Chandra S. Tiwari

IPC分类号： H01L23/00 ,  H01L21/66 ,  H01L25/065

CPC分类号： H01L24/05 ,  H01L22/32 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/03011 ,  H01L2224/0345 ,  H01L2224/03921 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13014 ,  H01L2224/13021 ,  H01L2224/13026 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/01074

摘要： Semiconductor devices having discretely located passivation material are disclosed herein. In one embodiment, a semiconductor device assembly can include a bond pad having a bonding surface with a process artifact. A passivation material can be positioned to at least partially fill a portion of the process artifact. A conductive structure can be positioned to extend across the bonding surface of the bond pad.

公开(公告)号：US10062656B2

公开(公告)日：2018-08-28

申请号：US15236526

申请日：2016-08-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chao-Ching Chang ,  Sheng-Chan Li ,  Wen-Jen Tsai ,  Chih-Hui Huang ,  Jian-Shin Tsai ,  Cheng-Yi Wu ,  Yi-Ming Lin ,  Min-Hui Lin

IPC分类号： H01L23/00

CPC分类号： H01L24/02 ,  H01L23/291 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/02251 ,  H01L2224/0226 ,  H01L2224/02331 ,  H01L2224/0237 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/03011 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03616 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05547 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05583 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/80001 ,  H01L2224/80895 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0504 ,  H01L2924/0544 ,  H01L2924/05442 ,  H01L2924/059 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A semiconductor device includes a substrate, a dielectric structure, a top metal layer and a bonding structure. The dielectric structure is disposed on the substrate. The top metal layer is disposed in the dielectric structure. The bonding structure is disposed on the dielectric structure and the top metal layer. The bonding structure includes a silicon oxide layer, a silicon oxy-nitride layer, a conductive bonding layer and a barrier layer. The silicon oxide layer is disposed on the dielectric structure. The silicon oxy-nitride layer covers the silicon oxide layer. The conductive bonding layer is disposed in the silicon oxide layer and the silicon oxy-nitride layer. The barrier layer covers a sidewall and a bottom of the conductive bonding layer.

公开(公告)号：US20170040274A1

公开(公告)日：2017-02-09

申请号：US15296770

申请日：2016-10-18

申请人： GLOBALFOUNDRIES Inc.

发明人： Luke ENGLAND ,  Christian KLEWER

IPC分类号： H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L24/05 ,  H01L23/522 ,  H01L24/03 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03011 ,  H01L2224/03616 ,  H01L2224/05551 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06133 ,  H01L2224/08121 ,  H01L2224/08123 ,  H01L2224/08145 ,  H01L2224/80013 ,  H01L2224/80194 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2224/80986 ,  H01L2224/94 ,  H01L2225/06527 ,  H01L2224/80001 ,  H01L2924/00014

摘要： Methods for preparing 3D integrated semiconductor devices and the resulting devices are disclosed. Embodiments include forming a first and a second bond pad on a first and a second semiconductor device, respectively, the first and the second bond pads each having plural metal segments, the metal segments of the first bond pad having a configuration different from a configuration of the metal segments of the second bond pad or having the same configuration as a configuration of the metal segments of the second bond pad but rotated with respect to the second bond pad; and bonding the first and second semiconductor devices together through the first and second bond pads.

摘要翻译： 公开了用于制备3D集成半导体器件和所得到的器件的方法。 实施例包括分别在第一和第二半导体器件上形成第一和第二接合焊盘，第一和第二接合焊盘分别具有多个金属段，第一接合焊盘的金属段具有不同于 第二接合焊盘的金属段或者具有与第二接合焊盘的金属段的构造相同的配置，但是相对于第二接合焊盘旋转; 以及通过所述第一和第二接合焊盘将所述第一和第二半导体器件接合在一起。

公开(公告)号：US09536848B2

公开(公告)日：2017-01-03

申请号：US14515969

申请日：2014-10-16

申请人： GLOBALFOUNDRIES Inc.

发明人： Luke England ,  Christian Klewer

IPC分类号： H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L23/522

CPC分类号： H01L24/05 ,  H01L23/522 ,  H01L24/03 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03011 ,  H01L2224/03616 ,  H01L2224/05551 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06133 ,  H01L2224/08121 ,  H01L2224/08123 ,  H01L2224/08145 ,  H01L2224/80013 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2224/80986 ,  H01L2224/94 ,  H01L2225/06527 ,  H01L2224/80001 ,  H01L2924/00014

摘要： Methods for preparing 3D integrated semiconductor devices and the resulting devices are disclosed. Embodiments include forming a first and a second bond pad on a first and a second semiconductor device, respectively, the first and the second bond pads each having plural metal segments, the metal segments of the first bond pad having a configuration different from a configuration of the metal segments of the second bond pad or having the same configuration as a configuration of the metal segments of the second bond pad but rotated with respect to the second bond pad; and bonding the first and second semiconductor devices together through the first and second bond pads.

摘要翻译： 公开了用于制备3D集成半导体器件和所得到的器件的方法。 实施例包括分别在第一和第二半导体器件上形成第一和第二接合焊盘，第一和第二接合焊盘分别具有多个金属段，第一接合焊盘的金属段具有不同于 第二接合焊盘的金属段或者具有与第二接合焊盘的金属段的构造相同的配置，但是相对于第二接合焊盘旋转; 以及通过所述第一和第二接合焊盘将所述第一和第二半导体器件接合在一起。

公开(公告)号：US20160111386A1

公开(公告)日：2016-04-21

申请号：US14515969

申请日：2014-10-16

申请人： Globalfoundries Inc.

发明人： Luke ENGLAND ,  Christian KLEWER

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L24/05 ,  H01L23/522 ,  H01L24/03 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03011 ,  H01L2224/03616 ,  H01L2224/05551 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06133 ,  H01L2224/08121 ,  H01L2224/08123 ,  H01L2224/08145 ,  H01L2224/80013 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2224/80986 ,  H01L2224/94 ,  H01L2225/06527 ,  H01L2224/80001 ,  H01L2924/00014

摘要： Methods for preparing 3D integrated semiconductor devices and the resulting devices are disclosed. Embodiments include forming a first and a second bond pad on a first and a second semiconductor device, respectively, the first and the second bond pads each having plural metal segments, the metal segments of the first bond pad having a configuration different from a configuration of the metal segments of the second bond pad or having the same configuration as a configuration of the metal segments of the second bond pad but rotated with respect to the second bond pad; and bonding the first and second semiconductor devices together through the first and second bond pads.

摘要翻译： 公开了用于制备3D集成半导体器件和所得到的器件的方法。 实施例包括分别在第一和第二半导体器件上形成第一和第二接合焊盘，第一和第二接合焊盘分别具有多个金属段，第一接合焊盘的金属段具有不同于 第二接合焊盘的金属段或者具有与第二接合焊盘的金属段的构造相同的配置，但是相对于第二接合焊盘旋转; 以及通过所述第一和第二接合焊盘将所述第一和第二半导体器件接合在一起。