公开(公告)号：US09806916B1

公开(公告)日：2017-10-31

申请号：US15490725

申请日：2017-04-18

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Vladimir M. Stojanovic ,  Fred F. Chen

IPC: H04L25/03 ,  H04L7/033 ,  H04L7/00 ,  H04B1/10

CPC classification number: H04L25/03019 ,  H04B1/1081 ,  H04L7/0058 ,  H04L7/0087 ,  H04L7/0331 ,  H04L25/03025 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03343 ,  H04L25/03885

Abstract: A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.

公开(公告)号：US09804931B2

公开(公告)日：2017-10-31

申请号：US14568768

申请日：2014-12-12

Applicant: Rambus Inc.

Inventor： Steven Woo ,  David Secker ,  Ravindranath Kollipara

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F11/14 ,  G06F1/12 ,  G06F11/20 ,  G06F11/16 ,  G06F13/42

CPC classification number: G06F11/1456 ,  G06F1/12 ,  G06F11/1666 ,  G06F11/20 ,  G06F11/2058 ,  G06F13/4234 ,  G06F2201/84

Abstract: Memory system enabling memory mirroring in single write operations for the primary and backup data storage. The memory system utilizes a memory channel including one or more latency groups, with each latency group encompassing a number of memory modules that have the same signal timing to the controller. A primary copy and a backup copy of a data element can be written to two memory modules in the same latency group of the channel and in a single write operation. The buses of the channel may have the same trace length to each of the memory modules within a latency group.

公开(公告)号：US09785365B1

公开(公告)日：2017-10-10

申请号：US14963098

申请日：2015-12-08

Applicant: Rambus Inc.

Inventor： Aws Shallal ,  Collins Williams ,  Dan Kunkel ,  William Wolf

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/0802 ,  G06F12/02 ,  G06F11/14

CPC classification number: G06F11/1446 ,  G06F3/0608 ,  G06F11/1448 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0868 ,  G06F13/28 ,  G06F2212/1024 ,  G06F2212/205 ,  G06F2212/214 ,  G06F2212/313

Abstract: The present invention is directed to memory systems. More specifically, embodiments of the present invention provide a memory system with a volatile memory, a persistent memory, and a controller. In a save operation, the controller copies contents of the volatile memory to the persistent memory as data units with their corresponding descriptor fields, where the descriptor fields include address information. In a restore operation, the controller copies data units from the persistent memory to their corresponding locations based on addresses stored at descriptor fields. There are other embodiments as well.

公开(公告)号：US20170287571A1

公开(公告)日：2017-10-05

申请号：US15506621

申请日：2015-08-17

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  John Eric Linstadt ,  Paul William Roukema

IPC: G11C29/44 ,  G11C11/401 ,  G11C29/02 ,  G11C5/04 ,  G11C29/52 ,  G11C29/00

CPC classification number: G11C29/4401 ,  G11C5/04 ,  G11C11/401 ,  G11C29/022 ,  G11C29/52 ,  G11C29/76 ,  G11C29/783 ,  G11C29/88 ,  G11C2029/4402

Abstract: A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic.

公开(公告)号：US09762434B2

公开(公告)日：2017-09-12

申请号：US14236572

申请日：2012-07-20

Applicant: Paul D. Franzon ,  John Wilson

Inventor： Paul D. Franzon ,  John Wilson

IPC: H04L12/24 ,  G06F11/20 ,  H04L1/22 ,  H03L7/18 ,  H03L7/23 ,  H04L1/00

CPC classification number: H04L41/0686 ,  G06F11/2007 ,  H03L7/18 ,  H03L7/23 ,  H04L1/0002 ,  H04L1/22 ,  H04L41/0659 ,  H04L41/0668

Abstract: A circuit is provided to facilitate temporal redundancy for inter-chip communication. When an inter-chip communication channel fails, data bits associated with the faulty channel are steered to a non-faulty channel and transmitted via the non-faulty channel together with data bits associated with the non-faulty channel at an increased data rate.

公开(公告)号：US09753521B2

公开(公告)日：2017-09-05

申请号：US14951150

申请日：2015-11-24

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton ,  Andrew M. Fuller

IPC: G06F1/04 ,  G06F1/08 ,  G06F1/32 ,  G11C7/04 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G06F13/16 ,  G06F1/12 ,  G06F3/06 ,  G06F9/38 ,  G06F12/0855 ,  G06F13/36

CPC classification number: G06F1/3237 ,  G06F1/12 ,  G06F1/3225 ,  G06F1/324 ,  G06F3/0604 ,  G06F3/0625 ,  G06F3/0629 ,  G06F3/0673 ,  G06F9/3836 ,  G06F12/0857 ,  G06F13/1689 ,  G06F13/36 ,  G06F2201/88 ,  G11C7/04 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/2254 ,  Y02D10/14

Abstract: In an integrated circuit device that outputs data values during respective transmit intervals defined by transitions of a transmit clock, the phase of the transmit clock is shifted by half a transmit interval to enable a timing calibration operation. Thereafter, a sequence of data values is transmitted to another integrated circuit device in response to the phase-shifted transmit clock and a samples of the sequence of data values are received from the other integrated circuit device. The received samples are compared with the sequence of data values to determine a phase update value, including comparing at least one received sample with two adjacent data values within the sequence of data values, and the phase of the transmit clock is incrementally advanced or retarded according to the phase update value.

公开(公告)号：US09748960B2

公开(公告)日：2017-08-29

申请号：US14456716

申请日：2014-08-11

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Brian S. Leibowitz ,  Hsuan-Jung Su ,  John Cronan Eble, III ,  Barry William Daly ,  Lei Luo ,  Teva J. Stone ,  John Wilson ,  Jihong Ren ,  Wayne D. Dettloff

IPC: H03L7/091 ,  H03L7/099 ,  H03L7/00 ,  G11C7/10 ,  G11C7/22 ,  H04L7/033 ,  H03L7/08 ,  H04L7/00 ,  G11C7/04

CPC classification number: H03L7/091 ,  G11C7/04 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  H03L7/00 ,  H03L7/0802 ,  H03L7/099 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0079 ,  H04L7/0087 ,  H04L7/033

Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

公开(公告)号：US09747230B2

公开(公告)日：2017-08-29

申请号：US14408955

申请日：2013-10-14

Applicant: Rambus Inc.

Inventor： Minghui Han ,  Amir Amirkhany ,  Ravindranath Kollipara ,  Ralf Michael Schmitt

IPC: G06F13/36 ,  G06F13/28 ,  G06F3/06 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10

CPC classification number: G06F13/28 ,  G06F3/0611 ,  G06F3/0635 ,  G06F3/0683 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1084

Abstract: A memory system includes a two memory modules and a memory controller. The memory modules each include at least a first memory package corresponding to a first number of memory ranks (e.g. one memory rank) and a second memory package corresponding to a second number of memory ranks (e.g. two memory ranks) that is greater than the first number of memory ranks. For each module, the memory packages may be asymmetrically staggered such that one memory package is further from the memory controller than the other memory package. The memory controller is coupled to the memory packages of both modules via a common data line and generates control information for controlling the on-die termination (ODT) of the memory packages.

公开(公告)号：US09747037B2

公开(公告)日：2017-08-29

申请号：US14951377

申请日：2015-11-24

Applicant: RAMBUS INC.

Inventor： Victor Cai

IPC: G06F1/18 ,  G06F3/06 ,  G11C5/04 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4093

CPC classification number: G06F3/061 ,  G06F1/185 ,  G06F3/0629 ,  G06F3/0683 ,  G11C5/04 ,  G11C11/4076 ,  G11C11/4082 ,  G11C11/4093

Abstract: An extended-height DIMM for use in a memory system having slots designed to receive DIMMs that comply with a JEDEC standard that specifies a maximum height for the DIMM and a maximum number of devices allowed to reside on the DIMM. The DIMM comprises a PCB having an edge connector designed to mate with a memory system slot and a height which is greater than the maximum height specified in the applicable standard, a plurality of memory devices which exceeds the maximum number of devices specified in the applicable standard, and a memory buffer, or a register control device and data buffers, which operates as an interface between a host controller's data and command/address busses and the memory devices. This arrangement enables the extended-height DIMM to provide greater memory capacity than would a DIMM which complies with the maximum height and maximum number of devices limits.

公开(公告)号：US09722539B2

公开(公告)日：2017-08-01

申请号：US14858965

申请日：2015-09-18

Applicant: Rambus Inc.

Inventor： Mohammad Hekmat ,  Reza Navid

IPC: H03B27/00 ,  H03L7/06 ,  H03L7/23 ,  H03L7/099

CPC classification number: H03B27/00 ,  H03L7/06 ,  H03L7/099 ,  H03L7/23

Abstract: A phase-locked loop circuit comprises a multi-phase oscillator having a plurality of coupled oscillators. A calibration module detects mismatches between frequency characteristics of the different oscillators in the phase-locked loop circuit during a calibration process. The calibration module then calibrates the various oscillators to compensate for the detected mismatch. Once calibrated, the phase-locked loop circuit can operate with little or no performance degradation despite the mismatch in frequency characteristics between the different oscillators.