Microelectronic package comprising offset conductive posts on compliant layer
    41.
    发明授权
    Microelectronic package comprising offset conductive posts on compliant layer 有权
    微电子封装包括柔性层上的偏移导电柱

    公开(公告)号:US08207604B2

    公开(公告)日:2012-06-26

    申请号:US10985126

    申请日:2004-11-10

    IPC分类号: H01L23/485

    摘要: A microelectronic package includes a mounting structure, a microelectronic element associated with the mounting structure, and a plurality of conductive posts physically connected to the mounting structure and electrically connected to the microelectronic element. The conductive posts project from the mounting structure in an upward direction, at least one of the conductive posts being an offset post. Each offset post has a base connected to the mounting structure, the base of each offset post defining a centroid. Each offset post also defines an upper extremity having a centroid, the centroid of the upper extremity being offset from the centroid of the base in a horizontal offset direction transverse to the upward direction. The mounting structure is adapted to permit tilting of each offset post about a horizontal axis so that the upper extremities may wipe across a contact pad of an opposing circuit board.

    摘要翻译: 微电子封装包括安装结构,与安装结构相关联的微电子元件以及物理连接到安装结构并电连接到微电子元件的多个导电柱。 导电柱从安装结构沿向上的方向突出,至少一个导电柱是偏移柱。 每个偏移柱具有连接到安装结构的基座,每个偏置柱的基部限定质心。 每个偏移柱还限定具有质心的上肢,上肢的质心在垂直于向上方向的水平偏移方向上偏离基部的质心。 安装结构适于允许每个偏移柱绕水平轴线倾斜,使得上端部可以擦过相对电路板的接触垫。

    DUAL WAFER SPIN COATING
    43.
    发明申请
    DUAL WAFER SPIN COATING 有权
    双面旋涂

    公开(公告)号:US20120152433A1

    公开(公告)日:2012-06-21

    申请号:US12974611

    申请日:2010-12-21

    IPC分类号: B32B37/06

    CPC分类号: H01L22/12 H01L21/67092

    摘要: A method of bonding a first substrate and a second substrate includes the steps of rotating first substrate with an adhesive mass thereon, and second substrate contacting the mass and overlying the first substrate, controlling a vertical height of a heated control platen spaced apart from and not contacting the second substrate so as to control a temperature of the adhesive mass, so as to at least one of bond the first and second substrates in alignment with one another, or achieve a sufficiently planar adhesive interface between the first and second substrates.

    摘要翻译: 接合第一基板和第二基板的方法包括以下步骤:使第一基板与其上的粘合剂质量物质旋转,第二基板接触物料并覆盖第一基板,控制加热的控制台板的垂直高度, 使所述第二基板接触以控制所述粘合剂物料的温度,以便使所述第一和第二基板彼此对准的至少一个接合,或在所述第一和第二基板之间实现足够平坦的粘合界面。

    Microelectronic assemblies having very fine pitch stacking
    49.
    发明授权
    Microelectronic assemblies having very fine pitch stacking 有权
    微电子组件具有非常细的间距堆积

    公开(公告)号:US08067267B2

    公开(公告)日:2011-11-29

    申请号:US11318164

    申请日:2005-12-23

    IPC分类号: H01L21/00

    摘要: A method of making a stacked microelectronic assembly includes providing a first microelectronic package that includes a first substrate having a first dielectric layer, conductive posts, and conductive traces extending along the surface of the first dielectric layer; providing a second microelectronic package including a second substrate that includes a second dielectric layer; securing a microelectronic element to one of the surfaces of at least one of the first or second substrates; and joining the conductive posts of the first substrate with the fusible masses of the second substrate. The posts may include a plurality of aligned posts which are aligned in a first row extending in a single orthogonal direction along a surface of the first substrate away from a portion of the first substrate that faces a face of the microelectronic element. The aligned posts are disposed beyond one of the edges of the microelectronic element.

    摘要翻译: 制造堆叠的微电子组件的方法包括提供第一微电子封装,其包括具有第一电介质层的第一衬底,导电柱和沿着第一电介质层的表面延伸的导电迹线; 提供包括第二衬底的第二微电子封装,所述第二衬底包括第二介电层; 将微电子元件固定到所述第一或第二基板中的至少一个的一个表面上; 以及将第一基板的导电柱与第二基板的可熔块接合。 柱可以包括多个对准的柱,其在沿着第一基板的表面沿着单个正交方向延伸的第一行中排列,远离第一基板的面对微电子元件的表面的部分。 对准的柱被设置在微电子元件的边缘之一之外。