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    BATTERY WITH SELF-PROGRAMMING FUSE
    41.
    发明申请
    BATTERY WITH SELF-PROGRAMMING FUSE 有权
    具有自编程保险丝的电池

    公开(公告)号：US20130183553A1

    公开(公告)日：2013-07-18

    申请号：US13349255

    申请日：2012-01-12

    申请人： Hariklia Deligianni ,  Harold J. Hovel ,  Fei Liu

    发明人： Hariklia Deligianni ,  Harold J. Hovel ,  Fei Liu

    IPC分类号： H01M10/42 ,  H01M4/04 ,  H01M2/20

    CPC分类号： H01M2/204 ,  H01G11/16 ,  H01M2/348 ,  H01M10/0436 ,  H01M10/052 ,  H01M10/0562 ,  H01M10/058 ,  H01M2200/103 ,  Y10T29/49108 ,  Y10T29/49115

    摘要： A useful lifetime of an energy storage device can be extended by providing a series connection of a battery cell and an self-programming fuse. A plurality of series connections of a battery cell and an self-programming fuse can then be connected in a parallel connection to expand the energy storage capacity of the energy storage device. Each self-programming fuse can be a strip of a metal semiconductor alloy material, which electromigrates when a battery cell is electrically shorted and causes increases in the amount of electrical current therethrough. Thus, each self-programming fuse is a self-programming circuit that opens once the battery cell within the same series connection is shorted.

    摘要翻译： 可以通过提供电池单元和自编程保险丝的串联连接来扩展能量存储装置的有用寿命。 然后可以并联连接电池单元和自编程保险丝的多个串联连接以扩大能量存储装置的能量存储容量。 每个自编程保险丝可以是金属半导体合金材料的条带，当电池单元电气短路并导致电流量增加时，电极会电流化。 因此，每个自编程保险丝是一个自编程电路，一旦同一串联连接中的电池单元短路，该自编程电路就会断开。

    Gallium Electrodeposition Processes and Chemistries
    43.
    发明申请
    Gallium Electrodeposition Processes and Chemistries 失效
    镓电沉积工艺和化学

    公开(公告)号：US20120055801A1

    公开(公告)日：2012-03-08

    申请号：US12874504

    申请日：2010-09-02

    申请人： Shafaat Ahmed ,  Hariklia Deligianni

    发明人： Shafaat Ahmed ,  Hariklia Deligianni

    IPC分类号： C25D3/54

    CPC分类号： C25D3/54 ,  C25D3/56

    摘要： Solutions and processes for electrodepositing gallium or gallium alloys includes a plating bath free of complexing agents including a gallium salt, an indium salt, a combination thereof, and a combination of any of the preceding salts with copper, an acid, and a solvent, wherein the pH of the solution is in a range selected from the group consisting of from about zero to about 2.6 and greater than about 12.6 to about 14. An optional metalloid may be included in the solution.

    摘要翻译： 用于电镀镓或镓合金的溶液和方法包括不含络合剂的镀浴，所述配合剂包括镓盐，铟盐，其组合以及任何前述盐与铜，酸和溶剂的组合，其中 溶液的pH在选自约0至约2.6且大于约12.6至约14的范围内。溶液中可包含任选的准金属。

    Complementary metal oxide semiconductor device with an electroplated metal replacement gate
    46.
    发明授权
    Complementary metal oxide semiconductor device with an electroplated metal replacement gate 失效
    具有电镀金属置换栅的互补金属氧化物半导体器件

    公开(公告)号：US07776680B2

    公开(公告)日：2010-08-17

    申请号：US11968885

    申请日：2008-01-03

    申请人： Veeraraghavan S. Basker ,  John M. Cotte ,  Hariklia Deligianni ,  Toshiharu Furukawa ,  Vamsi K. Paruchuri ,  William R. Tonti

    发明人： Veeraraghavan S. Basker ,  John M. Cotte ,  Hariklia Deligianni ,  Toshiharu Furukawa ,  Vamsi K. Paruchuri ,  William R. Tonti

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823842 ,  H01L29/517 ,  H01L29/66545

    摘要： Disclosed herein are embodiments of a method of forming a complementary metal oxide semiconductor (CMOS) device that has at least one high aspect ratio gate structure with a void-free and seam-free metal gate conductor layer positioned on top of a relatively thin high-k gate dielectric layer. These method embodiments incorporate a gate replacement strategy that uses an electroplating process to fill, from the bottom upward, a high-aspect ratio gate stack opening with a metal gate conductor layer. The source of electrons for the electroplating process is a current passed directly through the back side of the substrate. This eliminates the need for a seed layer and ensures that the metal gate conductor layer will be formed without voids or seams. Furthermore, depending upon the embodiment, the electroplating process is performed under illumination to enhance electron flow to a given area (i.e., to enhance plating) or in darkness to prevent electron flow to a given area (i.e., to prevent plating).

    摘要翻译： 本文公开了一种形成互补金属氧化物半导体（CMOS）器件的方法的实施例，该器件具有至少一个高纵横比栅极结构，其中无空隙和无缝的金属栅极导体层位于相对薄的高压 k栅介质层。 这些方法实施例包括栅极替换策略，其使用电镀工艺从底部向上填充具有金属栅极导体层的高纵横比栅极堆叠开口。 用于电镀工艺的电子源是直接通过衬底背面的电流。 这消除了对种子层的需要，并且确保金属栅极导体层将形成为没有空隙或接缝。 此外，根据实施例，电镀工艺在照明下进行，以增强电子流向给定区域（即，为了增强电镀）或在黑暗中以防止电子流向给定区域（即防止电镀）。

    VERTICAL PROFILE FinFET GATE FORMED VIA PLATING UPON A THIN GATE DIELECTRIC
    48.
    发明申请
    VERTICAL PROFILE FinFET GATE FORMED VIA PLATING UPON A THIN GATE DIELECTRIC 审中-公开
    垂直型材FinFET通过薄型电介质形成的FinFET栅极

    公开(公告)号：US20090321833A1

    公开(公告)日：2009-12-31

    申请号：US12145616

    申请日：2008-06-25

    申请人： Veeraraghaven S. Basker ,  Hariklia Deligianni ,  Toshiharu Furukawa ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

    发明人： Veeraraghaven S. Basker ,  Hariklia Deligianni ,  Toshiharu Furukawa ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/66795 ,  H01L29/785

    摘要： Methods of making vertical profile FinFET gate electrodes via plating upon a thin gate dielectric are disclosed. In one embodiment, a method for forming a transistor, comprises: providing a semiconductor topography comprising a semiconductor substrate and a semiconductor fin structure extending above the substrate; forming a gate dielectric across exposed surfaces of the semiconductor topography; patterning a mask upon the semiconductor topography such that only a select portion of the gate dielectric is exposed that defines where a gate electrode is to be formed; and plating a metallic material upon the select portion of the gate dielectric to form a gate electrode across a portion of the fin structure.

    摘要翻译： 公开了通过在薄栅极电介质上电镀制造垂直轮廓FinFET栅电极的方法。 在一个实施例中，一种用于形成晶体管的方法包括：提供包括半导体衬底和在衬底上方延伸的半导体鳍片结构的半导体形貌; 在半导体拓扑的暴露表面上形成栅极电介质; 在半导体形貌上图案化掩模，使得仅限定限定要形成栅电极的位置的栅极电介质的选择部分; 以及在所述栅极电介质的所述选择部分上镀覆金属材料以在所述鳍结构的一部分上形成栅电极。