公开(公告)号：US20090008796A1

公开(公告)日：2009-01-08

申请号：US11965252

申请日：2007-12-27

申请人： Kian Teng Eng ,  Wolfgang Johannes HETZEL ,  Werner Josef REISS ,  Florian AMMER ,  Yong Chuan KOH ,  Jimmy SIAT

发明人： Kian Teng Eng ,  Wolfgang Johannes HETZEL ,  Werner Josef REISS ,  Florian AMMER ,  Yong Chuan KOH ,  Jimmy SIAT

IPC分类号： H01L23/49 ,  H01L21/44

CPC分类号： H01L25/0657 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/48475 ,  H01L2224/48479 ,  H01L2224/48505 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48747 ,  H01L2224/48824 ,  H01L2224/48839 ,  H01L2224/48847 ,  H01L2224/49 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85051 ,  H01L2224/85375 ,  H01L2225/0651 ,  H01L2225/06582 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/48471 ,  H01L2924/00015 ,  H01L2924/01049 ,  H01L2224/4554 ,  H01L2924/00012 ,  H01L2924/206 ,  H01L2224/43848

摘要： Provided is a semiconductor package, and a method for constructing the same, including a first substrate, a first semiconductor chip attached to the first substrate, and a first copper wire. At least one of the first substrate and the first semiconductor chip has an Organic Solderability Preservative (OSP) material coated on at least a portion of one surface, and the first copper wire is wire bonded through the OSP material to the first substrate and the first semiconductor chip.

摘要翻译： 提供一种半导体封装及其构造方法，包括第一基板，附接到第一基板的第一半导体芯片和第一铜线。 第一衬底和第一半导体芯片中的至少一个具有涂覆在一个表面的至少一部分上的有机可焊性防腐剂（OSP）材料，并且第一铜线通过OSP材料引线键合到第一衬底，并且第一衬底 半导体芯片

公开(公告)号：US20080303163A1

公开(公告)日：2008-12-11

申请号：US12133376

申请日：2008-06-05

申请人： Hao LIU ,  Yi Sheng Anthony SUN ,  Ravi Kanth KOLAN ,  Chin Hock TOH

发明人： Hao LIU ,  Yi Sheng Anthony SUN ,  Ravi Kanth KOLAN ,  Chin Hock TOH

IPC分类号： H01L21/768 ,  H01L21/50 ,  H01L23/488

CPC分类号： H01L24/80 ,  H01L21/768 ,  H01L21/76898 ,  H01L24/11 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68377 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/1132 ,  H01L2224/1147 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16237 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83856 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A method for preparing a die for packaging is disclosed. A die having first and second major surfaces is provided. Vias and a mask layer are formed on the first major surface of the die. The mask includes mask openings that expose the vias. The mask openings are filled with a conductive material. The method includes reflowing to at least partially fill the vias and contact openings to form via contacts in the vias and surface contacts in the mask openings.

摘要翻译： 公开了一种用于制造包装用模具的方法。 提供具有第一和第二主表面的模具。 在模具的第一主表面上形成通孔和掩模层。 掩模包括露出通孔的掩模开口。 掩模开口用导电材料填充。 该方法包括回流以至少部分地填充通孔和接触开口，以在掩模开口中的通孔和表面接触中形成通孔接触。

公开(公告)号：US20080199985A1

公开(公告)日：2008-08-21

申请号：US12113968

申请日：2008-05-02

申请人： Danny Vallejo Retuta ,  Hien Boon Tan ,  Susanto Tanary ,  Anthony Yi Sheng Sun ,  Soon Huat James Tan

发明人： Danny Vallejo Retuta ,  Hien Boon Tan ,  Susanto Tanary ,  Anthony Yi Sheng Sun ,  Soon Huat James Tan

IPC分类号： H01L21/00

CPC分类号： H01L21/4842 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49548 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor package includes a plurality of first leads, each with a top outer portion removed from the lead and an outer end, and a plurality of second leads, each with a bottom outer portion removed from the lead and an outer end. The first and second leads alternate with each other along an edge of the package. Also, the outer ends of the first leads form a first row along the edge of the package and the outer ends of the second leads form a second row along the edge of the package. In one embodiment, the first and second rows are parallel to each other and an encapsulant covers at least a portion of the first and second leads.

摘要翻译： 半导体封装包括多个第一引线，每个第一引线具有从引线除去的顶部外部部分和外端，以及多个第二引线，每个引线具有从引线除去的底部外部部分和外部端部。 第一和第二引线沿着封装的边缘彼此交替。 此外，第一引线的外端沿着封装的边缘形成第一排，并且第二引线的外端沿着封装的边缘形成第二排。 在一个实施例中，第一和第二行彼此平行，并且密封剂覆盖第一和第二引线的至少一部分。

公开(公告)号：US07323769B2

公开(公告)日：2008-01-29

申请号：US11429248

申请日：2006-05-08

申请人： Hien Boon Tan ,  Anthony Yi Sheng Sun ,  Francis Koon Seong Poh

发明人： Hien Boon Tan ,  Anthony Yi Sheng Sun ,  Francis Koon Seong Poh

IPC分类号： H01L23/495 ,  H01L23/48

CPC分类号： H01L24/32 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/4951 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/4943 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/92165 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/18165 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： An integrated circuit package is disclosed. The package comprises a plurality of leads, each lead having a first face and a second face opposite to the first face. The package also comprises a die pad having a first face and a second face opposite to the first face. The second face of the die pad is orthogonally offset from the second face of the leads so that the second face of the die pad and the second face of the leads are not coplanar. The package also comprises an integrated circuit chip substantially laterally disposed between the plurality of leads, and having a first face and a second face opposite to the first face. The first face of the integrated circuit chip is proximate to the second face of the die pad and the first face of the integrated circuit chip is coupled to the second face of the die pad. The package further comprises a plurality of wires that link the plurality of leads to the integrated circuit chip. Each of the wires has a first end electrically conductively joined to the first face of the integrated circuit chip. The first end of the wire, therefore, is disposed between a plane defined by the second face of the die pad and a plane defined by the first face of the integrated circuit chip. Each of the wires also has a second end electrically conductively joined to the first face of one of the leads. The second end of the wire, therefore, is disposed between a plane defined by a first face of the die pad and a plane defined by the first face of the lead to which it is joined.

摘要翻译： 公开了一种集成电路封装。 该包装包括多个引线，每个引线具有第一面和与该第一面相对的第二面。 封装还包括具有第一面和与第一面相对的第二面的管芯焊盘。 管芯焊盘的第二面与引线的第二面正交地偏移，使得管芯焊盘的第二面和引线的第二面不共面。 封装还包括基本上横向设置在多个引线之间的集成电路芯片，并且具有与第一面相对的第一面和第二面。 集成电路芯片的第一面靠近芯片焊盘的第二面，并且集成电路芯片的第一面耦合到管芯焊盘的第二面。 封装还包括将多个引线连接到集成电路芯片的多个导线。 每根导线具有导电地连接到集成电路芯片的第一面的第一端。 因此，线的第一端设置在由芯片焊盘的第二面限定的平面和由集成电路芯片的第一面限定的平面之间。 每个电线还具有导电地连接到一个引线的第一面的第二端。 因此，线的第二端设置在由芯片焊盘的第一面限定的平面和由其连接的引线的第一面限定的平面之间。

公开(公告)号：US09136142B2

公开(公告)日：2015-09-15

申请号：US14257017

申请日：2014-04-21

申请人： UNITED TEST AND ASSEMBLY CENTER LTD.

发明人： Chuen Khiang Wang ,  Nathapong Suthiwongsunthorn ,  Kriangsak Sae Le ,  Antonio Jr B Dimaano ,  Catherine Bee Liang Ng ,  Richard Te Gan ,  Kian Teng Eng

IPC分类号： H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L25/03 ,  H01L25/10 ,  H01L25/16 ,  H01L23/36 ,  H01L23/48 ,  H01L23/00

CPC分类号： H01L23/49861 ,  H01L21/2885 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/4832 ,  H01L21/4839 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/481 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49534 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.

摘要翻译： 公开了一种设备。 该装置包括具有第一和第二主表面的载体衬底。 第一表面包括管芯区域和接触焊盘，第二表面包括封装接触。 载体衬底包括图案化引线框架，其将导电迹线和具有通孔触点的通孔级限定在线路电平。 图案化引线框架提供接触焊盘和封装触点之间的互连。 载体衬底还包括隔离导电迹线和通孔触点的电介质层。 该装置包括安装在第一表面的管芯区域上的管芯。

公开(公告)号：US08916422B2

公开(公告)日：2014-12-23

申请号：US13831964

申请日：2013-03-15

申请人： United Test and Assembly Center Ltd.

发明人： Chuen Khiang Wang

IPC分类号： H01L21/00 ,  H01L23/498 ,  H01L21/768 ,  H05K1/02 ,  H01L21/56

CPC分类号： H01L23/5384 ,  H01L21/4832 ,  H01L21/56 ,  H01L21/568 ,  H01L23/28 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49866 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/73265 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/09 ,  H05K1/115 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： Package substrate, semiconductor packages and methods for forming a semiconductor package are presented. The package substrate includes a base substrate having first and second major surfaces and a plurality of via contacts extending through the first to the second major surfaces of the base substrate. A first conductive layer having a plurality of openings is disposed over the first surface of the base substrate and via contacts. The openings are configured to match conductive trace layout of the package substrate. Conductive traces are disposed over the first conductive layer. The conductive traces are directly coupled to the via contacts through some of the openings of the first conductive layer.

摘要翻译： 提供封装衬底，半导体封装以及用于形成半导体封装的方法。 封装衬底包括具有第一和第二主表面的基底衬底和延伸穿过基底衬底的第一至第二主表面的多个通孔触头。 具有多个开口的第一导电层设置在基底基板的第一表面上并且经由触点。 开口被配置成匹配封装衬底的导电迹线布局。 导电迹线设置在第一导电层上。 导电迹线通过第一导电层的一些开口直接耦合到通孔触点。

公开(公告)号：US08860079B2

公开(公告)日：2014-10-14

申请号：US13467050

申请日：2012-05-09

申请人： Catherine Bee Liang Ng ,  Kriangsak Sae Le ,  Chuen Khiang Wang ,  Nathapong Suthiwongsunthorn

发明人： Catherine Bee Liang Ng ,  Kriangsak Sae Le ,  Chuen Khiang Wang ,  Nathapong Suthiwongsunthorn

IPC分类号： H01L21/56 ,  H01L23/48 ,  H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L23/3128 ,  H01L21/561 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/20 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48145 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： Semiconductor packages and methods of forming a semiconductor package are disclosed. The method includes providing at least one die having first and second surfaces. The second surface of the die includes a plurality of conductive pads. A permanent carrier is provided and the at least one die is attached to the permanent carrier. The first surface of the at least one die is facing the permanent carrier. A cap having first and second surfaces is formed to encapsulate the at least one die. The first surface of the cap contacts the permanent carrier and the second surface of the cap is disposed at a different plane than the second surface of the die.

摘要翻译： 公开了半导体封装和形成半导体封装的方法。 该方法包括提供具有第一表面和第二表面的至少一个模具。 管芯的第二表面包括多个导电焊盘。 提供永久性载体并且至少一个管芯附接到永久性载体。 至少一个管芯的第一表面面向永久性载体。 形成具有第一和第二表面的盖以封装至少一个管芯。 盖的第一表面与永久性载体接触，并且盖的第二表面设置在与模具的第二表面不同的平面上。

公开(公告)号：US20140264792A1

公开(公告)日：2014-09-18

申请号：US14094763

申请日：2013-12-02

申请人： United Test and Assembly Center Ltd.

发明人： Yong Bo YANG ,  Chun Hong WO

IPC分类号： H01L21/768 ,  H01L23/495

CPC分类号： H01L23/562 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/565 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/142 ,  H01L23/147 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L24/81 ,  H01L2021/60022 ,  H01L2224/10175 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/30505 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2924/15311 ,  H01L2924/19105 ,  H05K3/0023 ,  H05K3/0041 ,  H05K3/107 ,  H05K3/341 ,  H05K3/3452 ,  H05K3/4007 ,  H01L2924/00014 ,  H01L2924/00

摘要： Semiconductor packages and methods for forming a semiconductor package are presented. The method includes providing a package substrate having first and second major surfaces. The package substrate includes at least one substrate layer having at least one cavity. Interconnect structure is formed. At least one conductive stud is formed within the cavity and a conductive trace and a connection pad are formed over the first major surface of the package substrate and are coupled to top surface of the conductive stud. A package pad is formed and is directly coupled to the conductive stud. A die having conductive contacts on its first or second surface is provided. The conductive contacts of the die are electrically coupled to the interconnect structure. A cap is formed over the package substrate to encapsulate the die.

摘要翻译： 提出了用于形成半导体封装的半导体封装和方法。 该方法包括提供具有第一和第二主表面的封装衬底。 封装衬底包括至少一个具有至少一个空腔的衬底层。 互连结构形成。 在空腔内形成至少一个导电柱，并且导电迹线和连接焊盘形成在封装衬底的第一主表面之上并且耦合到导电柱的顶表面。 形成封装焊盘并且直接耦合到导电螺柱。 提供了在其第一或第二表面上具有导电接触的裸片。 管芯的导电触点电连接到互连结构。 在封装基板上形成盖以封装模具。

公开(公告)号：US08829666B2

公开(公告)日：2014-09-09

申请号：US13295097

申请日：2011-11-14

申请人： Catherine Bee Liang Ng ,  Kriangsak Sae Le ,  Chuen Khiang Wang ,  Nathapong Suthiwongsunthorn

发明人： Catherine Bee Liang Ng ,  Kriangsak Sae Le ,  Chuen Khiang Wang ,  Nathapong Suthiwongsunthorn

IPC分类号： H01L23/02

CPC分类号： H01L23/3128 ,  H01L21/561 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/20 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/81

摘要： Semiconductor packages and methods of forming a semiconductor package are disclosed. The method includes providing at least one die having first and second surfaces. The second surface of the die includes a plurality of conductive pads. A support carrier is provided and the at least one die is attached to the support carrier. The first surface of the at least one die is facing the support carrier. A cap having first and second surfaces is formed to encapsulate the at least one die. The second surface of the cap is disposed at a different plane than the second surface of the die.

摘要翻译： 公开了半导体封装和形成半导体封装的方法。 该方法包括提供具有第一表面和第二表面的至少一个模具。 管芯的第二表面包括多个导电焊盘。 提供支撑载体并且将至少一个管芯附接到支撑载体。 所述至少一个管芯的第一表面面向支撑载体。 形成具有第一和第二表面的盖以封装至少一个管芯。 帽的第二表面设置在与模具的第二表面不同的平面上。

公开(公告)号：US08816482B2

公开(公告)日：2014-08-26

申请号：US12330681

申请日：2008-12-09

申请人： Saravuth Sirinorakul ,  Kasemsan Kongthaworn

发明人： Saravuth Sirinorakul ,  Kasemsan Kongthaworn

IPC分类号： H01L23/495 ,  H01L21/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L23/49548 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49551 ,  H01L23/49572 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A flip-chip leadframe semiconductor package designed to improve mold flow around the leadframe and semiconductor die. An embodiment of the semiconductor package includes a leadframe, a semiconductor die attached to the leadframe, and an encapsulant covering the leadframe and semiconductor die, wherein a portion of the leadframe that is attached to the semiconductor die is below a portion of the leadframe that enters the encapsulant.

摘要翻译： 一种倒装芯片引线框半导体封装，旨在改善引线框和半导体芯片周围的模具流动。 半导体封装的实施例包括引线框架，附接到引线框架的半导体管芯以及覆盖引线框架和半导体管芯的密封剂，其中附接到半导体管芯的引线框架的一部分低于进入的引线框架的一部分 密封剂。