公开(公告)号：US20120306080A1

公开(公告)日：2012-12-06

申请号：US13298046

申请日：2011-11-16

Applicant: Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Kuo-Ching Hsu ,  Cheng-Chieh Hsieh ,  Ying-Ching Shih ,  Po-Hao Tsai ,  Cheng-Lin Huang ,  Jing-Cheng Lin

Inventor： Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Kuo-Ching Hsu ,  Cheng-Chieh Hsieh ,  Ying-Ching Shih ,  Po-Hao Tsai ,  Cheng-Lin Huang ,  Jing-Cheng Lin

IPC: H01L23/52

CPC classification number: H01L24/11 ,  H01L23/147 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/04 ,  H01L25/50 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/10145 ,  H01L2224/10156 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11831 ,  H01L2224/13017 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13565 ,  H01L2224/13578 ,  H01L2224/13686 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/3651 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01047 ,  H01L2924/049 ,  H01L2924/053 ,  H01L2924/00

Abstract: A package component is free from active devices therein. The package component includes a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a metal pillar having a top surface over a top surface of the top dielectric layer. The metal pillar is electrically coupled to the through-via. A diffusion barrier is over the top surface of the metal pillar. A solder cap is disposed over the diffusion barrier.

Abstract translation: 封装组件不含其中的有源器件。 封装部件包括衬底，衬底中的通孔，衬底上的顶部电介质层和在顶部电介质层的顶表面上方具有顶表面的金属柱。 金属柱电连接到通孔。 扩散阻挡层在金属支柱的上表面之上。 焊料帽设置在扩散阻挡层上。

公开(公告)号：US08319349B2

公开(公告)日：2012-11-27

申请号：US13342583

申请日：2012-01-03

Applicant: Hsien-Pin Hu ,  Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Hung-Jung Tu

Inventor： Hsien-Pin Hu ,  Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Hung-Jung Tu

IPC: H01L23/48

CPC classification number: H01L21/561 ,  H01L21/486 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/05001 ,  H01L2224/05027 ,  H01L2224/05571 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.

公开(公告)号：US20120128457A1

公开(公告)日：2012-05-24

申请号：US12954180

申请日：2010-11-24

Applicant: Hsin Chang ,  Hsin-Yu Chen ,  Fang Wen Tsai ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Hsin Chang ,  Hsin-Yu Chen ,  Fang Wen Tsai ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: B65G1/133 ,  B25J18/00

CPC classification number: H01L21/6875 ,  B65G47/90 ,  H01L21/68707 ,  Y10T74/20305

Abstract: An apparatus includes a robot arm, and a plurality of guide pins mounted on the robot arm. Each of the plurality of guide pins includes a plurality of wafer supports at different levels, with each of the plurality of wafer supports configured to support and center a wafer having a size different from wafers configured to be supported and centered by remaining ones of the plurality of wafer supports

Abstract translation: 一种装置包括机器人臂和安装在机器人手臂上的多个引导销。 多个引导销中的每一个包括多个不同级别的晶片支架，其中多个晶片支撑件中的每一个被配置为支撑和定心具有不同晶圆尺寸的晶片，所述晶片被配置为被多个晶圆支撑的中心部分支撑并居中 的晶片支架

公开(公告)号：US20120045611A1

公开(公告)日：2012-02-23

申请号：US12858211

申请日：2010-08-17

Applicant: Ying-Ching Shih ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Ying-Ching Shih ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L23/12 ,  B32B3/24 ,  B32B3/26 ,  B32B38/10 ,  H01L21/50 ,  B32B37/02 ,  B32B37/12 ,  B32B17/06 ,  B32B7/12

CPC classification number: G07F17/3213 ,  B32B17/10 ,  B32B37/1207 ,  B32B37/182 ,  B32B37/185 ,  B32B2457/14 ,  H01L21/6835 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

Abstract: A composite carrier structure for manufacturing semiconductor devices is provided. The composite carrier structure utilizes multiple carrier substrates, e.g., glass or silicon substrates, coupled together by interposed adhesive layers. The composite carrier structure may be attached to a wafer or a die for, e.g., backside processing, such as thinning processes. In an embodiment, the composite carrier structure comprises a first carrier substrate having through-substrate vias formed therethrough. The first substrate is attached to a second substrate using an adhesive such that the adhesive may extend into the through-substrate vias.

Abstract translation: 提供了一种用于制造半导体器件的复合载体结构。 复合载体结构利用多个载体衬底，例如玻璃或硅衬底，通过插入的粘合剂层耦合在一起。 复合载体结构可以附接到晶片或模具，用于例如背面处理，例如变薄处理。 在一个实施例中，复合载体结构包括具有贯穿其中形成的贯通基板通孔的第一载体基板。 使用粘合剂将第一衬底附接到第二衬底，使得粘合剂可以延伸到贯穿衬底通孔中。

公开(公告)号：US20120025368A1

公开(公告)日：2012-02-02

申请号：US12847802

申请日：2010-07-30

Applicant: Yan-Fu Lin ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Yan-Fu Lin ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L23/544 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L21/563 ,  H01L23/49838 ,  H01L23/544 ,  H01L24/11 ,  H01L24/81 ,  H01L2223/54413 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2223/54486 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/73204 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

Abstract: A system and method for determining underfill expansion is provided. An embodiment comprises forming cover marks along a top surface of a substrate, attaching a semiconductor substrate to the top surface of the substrate, placing an underfill material between the semiconductor substrate and the substrate, and then using the cover marks to determine the expansion of the underfill over the top surface of the substrate. Additionally, cover marks may also be formed along a top surface of the semiconductor substrate, and the cover marks on both the substrate and the semiconductor substrate may be used together as alignment marks during the alignment of the substrate and the semiconductor substrate.

Abstract translation: 提供了一种用于确定底部填充膨胀的系统和方法。 一个实施例包括沿着衬底的顶表面形成覆盖标记，将半导体衬底附接到衬底的顶表面，将底部填充材料放置在半导体衬底和衬底之间，然后使用覆盖标记来确定 底部填充在基材的顶表面上。 此外，也可以沿着半导体衬底的顶表面形成覆盖标记，并且衬底和半导体衬底上的覆盖标记可以在衬底和半导体衬底的对准期间一起用作对准标记。

公开(公告)号：US20110316201A1

公开(公告)日：2011-12-29

申请号：US12822880

申请日：2010-06-24

Applicant: Lin-Chih Huang ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Lin-Chih Huang ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: B06B1/00 ,  H01L21/56 ,  B29C45/07

CPC classification number: H01L21/56 ,  H01L21/561 ,  H01L24/94 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

Abstract: In accordance with an embodiment, a molding apparatus comprises a screen having a planar top surface; a recess in the screen and extending below the planar top surface; a blade capable of traversing the planar top surface; and a molding compound applicator. Another embodiment is a method for molding. The method comprises providing a substrate in a confined volume with an open top surface, applying molding compound in the confined volume, and traversing the open top surface with a blade thereby forming the molding compound to have a planar surface that is co-planar with the open top surface. The substrate has at least one semiconductor die adhered to the substrate.

Abstract translation: 根据实施例，成型设备包括具有平坦顶表面的筛网; 屏幕中的凹槽并在平面顶表面下方延伸; 能够穿过平面顶表面的刀片; 和模塑料涂布器。 另一实施例是一种模制方法。 该方法包括在约束体积中提供具有敞开顶部表面的基底，在约束体积中施加模塑料，并用刀片横穿开放的顶部表面，从而形成模制化合物以具有与该平坦表面共面的平坦表面 开顶表面。 衬底具有至少一个半导体管芯粘附到衬底上。

公开(公告)号：US20110309647A1

公开(公告)日：2011-12-22

申请号：US12818022

申请日：2010-06-17

Applicant: Ku-Feng Yang ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Chen-Hua Yu

Inventor： Ku-Feng Yang ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC: B25J15/06 ,  B66C1/02

CPC classification number: H01L21/67346 ,  H01L21/6838 ,  H01L21/68785

Abstract: An apparatus for supporting a wafer includes a base, and a gas-penetration layer. The gas-penetration layer and a portion of the base directly underlying the gas-penetration layer form a gas passage therebetween. The gas passage is configured to be sealed by the wafer placed directly over the gas-penetration layer. The apparatus further includes a valve connected to the gas passage.

Abstract translation: 用于支撑晶片的装置包括基座和气体穿透层。 气体渗透层和直接位于气体穿透层下方的基底的一部分在它们之间形成气体通道。 气体通道被直接设置在气体穿透层上方的晶片密封。 该装置还包括连接到气体通道的阀。

公开(公告)号：US20110266691A1

公开(公告)日：2011-11-03

申请号：US12769251

申请日：2010-04-28

Applicant: Jing-Cheng Lin ,  Ku-Feng Yang

Inventor： Jing-Cheng Lin ,  Ku-Feng Yang

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/76816 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/49827 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/13025 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14181 ,  H01L2224/73204 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2224/05552

Abstract: A device includes a substrate, and a plurality of dielectric layers over the substrate. A plurality of metallization layers is formed in the plurality of dielectric layers, wherein at least one of the plurality of metallization layers comprises a metal pad. A through-substrate via (TSV) extends from the top level of the plurality of the dielectric layers to a bottom surface of the substrate. A deep conductive via extends from the top level of the plurality of dielectric layers to land on the metal pad. A metal line is formed over the top level of the plurality of dielectric layers and interconnecting the TSV and the deep conductive via.

Abstract translation: 一种器件包括衬底和在衬底上的多个电介质层。 多个金属化层形成在多个电介质层中，其中多个金属化层中的至少一个包括金属焊盘。 贯穿衬底通孔（TSV）从多个电介质层的顶层延伸到衬底的底表面。 深导电通孔从多个电介质层的顶层延伸到金属焊盘上。 金属线形成在多个电介质层的顶层上并且互连TSV和深导电通孔。

公开(公告)号：US20100163842A1

公开(公告)日：2010-07-01

申请号：US12345332

申请日：2008-12-29

Applicant: Li-Shyue Lai ,  Jing-Cheng Lin

Inventor： Li-Shyue Lai ,  Jing-Cheng Lin

IPC: H01L29/15 ,  H01L21/20

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795

Abstract: A method of forming an integrated circuit structure includes forming a first insulation region and a second insulation region in a semiconductor substrate and facing each other; and forming an epitaxial semiconductor region having a reversed T-shape. The epitaxial semiconductor region includes a horizontal plate including a bottom portion between and adjoining the first insulation region and the second insulation region, and a fin over and adjoining the horizontal plate. The bottom of the horizontal plate contacts the semiconductor substrate. The method further includes forming a gate dielectric on a top surface and at least top portions of sidewalls of the fin; and forming a gate electrode over the gate dielectric.

Abstract translation: 形成集成电路结构的方法包括：在半导体衬底中形成第一绝缘区域和第二绝缘区域并彼此面对; 以及形成具有反向T形的外延半导体区域。 外延半导体区域包括水平板，该水平板包括在第一绝缘区域和第二绝缘区域之间并邻接第一绝缘区域之间的底部，以及在水平板上并邻接的鳍状物。 水平板的底部接触半导体衬底。 该方法还包括在鳍的顶表面和至少顶部的顶部形成栅电介质; 以及在所述栅极电介质上形成栅电极。

公开(公告)号：US20100065924A1

公开(公告)日：2010-03-18

申请号：US12211464

申请日：2008-09-16

Applicant: Jing-Cheng Lin ,  Chen-Hua Yu

Inventor： Jing-Cheng Lin ,  Chen-Hua Yu

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/66636 ,  H01L21/2254 ,  H01L21/324 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/49 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

Abstract: A semiconductor device and a method of manufacturing are provided. A substrate has a gate stack formed thereon. Ultra-shallow junctions are formed by depositing an atomic layer of a dopant and performing an anneal to diffuse the dopant into the substrate on opposing sides of the gate stack. The substrate may be recessed prior to forming the atomic layer and the recess may be filled by an epitaxial process. The depositing, annealing, and, if used, epitaxial growth may be repeated a plurality of times to achieve the desired junctions. Source/drain regions are also provided on opposing sides of the gate stack.

Abstract translation: 提供半导体器件和制造方法。 基板上形成有栅叠层。 通过沉积掺杂剂的原子层并执行退火来形成超浅结，以将掺杂剂扩散到栅叠层的相对侧上的衬底中。 衬底可以在形成原子层之前被凹进，并且凹槽可以通过外延工艺填充。 可以重复沉积，退火和（如果使用）外延生长以实现所需的结。 源极/漏极区域也设置在栅极堆叠的相对侧上。