公开(公告)号：US10115701B2

公开(公告)日：2018-10-30

申请号：US14316561

申请日：2014-06-26

Applicant: STATS ChipPAC, Ltd.

Inventor： Xing Zhao ,  Duk Ju Na ,  Siew Joo Tan ,  Pandi C. Marimuthu

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/78 ,  H01L21/768 ,  H01L25/00

Abstract: A semiconductor device has a semiconductor wafer and a conductive via formed through the semiconductor wafer. A portion of the semiconductor wafer is removed such that a portion of the conductive via extends above the semiconductor wafer. A first insulating layer is formed over the conductive via and semiconductor wafer. A second insulating layer is formed over the first insulating layer. The first insulating layer includes an inorganic material and the second insulating layer includes an organic material. A portion of the first and second insulating layers is removed simultaneously from over the conductive via by chemical mechanical polishing (CMP). Alternatively, a first insulating layer including an organic material is formed over the conductive via and semiconductor wafer. A portion of the first insulating layer is removed by CMP. A conductive layer is formed over the conductive via and first insulating layer. The conductive layer is substantially planar.

公开(公告)号：US09721922B2

公开(公告)日：2017-08-01

申请号：US14139614

申请日：2013-12-23

Applicant: STATS ChipPAC, Ltd.

Inventor： Pandi C. Marimuthu ,  Yaojian Lin ,  Won Kyoung Choi ,  Il Kwon Shim

IPC: H01L29/66 ,  H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L25/0652 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has a first conductive layer including a plurality of conductive traces. The first conductive layer is formed over a substrate. The conductive traces are formed with a narrow pitch. A first semiconductor die and second semiconductor die are disposed over the first conductive layer. A first encapsulant is deposited over the first and second semiconductor die. The substrate is removed. A second encapsulant is deposited over the first encapsulant. A build-up interconnect structure is formed over the first conductive layer and second encapsulant. The build-up interconnect structure includes a second conductive layer. A first passive device is disposed in the first encapsulant. A second passive device is disposed in the second encapsulant. A vertical interconnect unit is disposed in the second encapsulant. A third conductive layer is formed over second encapsulant and electrically connected to the build-up interconnect structure via the vertical interconnect unit.

公开(公告)号：US09721921B2

公开(公告)日：2017-08-01

申请号：US15012346

申请日：2016-02-01

Applicant: STATS ChipPAC, Ltd.

Inventor： KyungMoon Kim ,  KooHong Lee ,  JaeHak Yee ,  YoungChul Kim ,  Lan Hoang ,  Pandi C. Marimuthu ,  Steve Anderson ,  HunTeak Lee ,  HeeJo Chi

IPC: H01L21/44 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L24/97 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11002 ,  H01L2224/1134 ,  H01L2224/13023 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/7598 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00012

Abstract: A semiconductor device has a plurality of semiconductor die disposed over a carrier. An electrical interconnect, such as a stud bump, is formed over the semiconductor die. The stud bumps are trimmed to a uniform height. A substrate includes a bump over the substrate. The electrical interconnect of the semiconductor die is bonded to the bumps of the substrate while the semiconductor die is disposed over the carrier. An underfill material is deposited between the semiconductor die and substrate. Alternatively, an encapsulant is deposited over the semiconductor die and substrate using a chase mold. The bonding of stud bumps of the semiconductor die to bumps of the substrate is performed using gang reflow or thermocompression while the semiconductor die are in reconstituted wafer form and attached to the carrier to provide a high throughput of the flipchip type interconnect to the substrate.

公开(公告)号：US09721862B2

公开(公告)日：2017-08-01

申请号：US14036525

申请日：2013-09-25

Applicant: STATS ChipPAC, Ltd.

Inventor： Byung Joon Han ,  Il Kwon Shim ,  Yaojian Lin ,  Pandi C. Marimuthu

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L24/96 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3114 ,  H01L24/19 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/03

Abstract: A semiconductor device includes a standardized carrier. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. The semiconductor wafer is singulated through a first portion of the base semiconductor material to separate the semiconductor die. The semiconductor die are disposed over the standardized carrier. A size of the standardized carrier is independent from a size of the semiconductor die. An encapsulant is deposited over the standardized carrier and around the semiconductor die. An interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The semiconductor device is singulated through the encapsulant. Encapsulant remains disposed on a side of the semiconductor die. Alternatively, the semiconductor device is singulated through a second portion of the base semiconductor and through the encapsulant to remove the second portion of the base semiconductor and encapsulant from the side of the semiconductor die.

公开(公告)号：US20160300797A1

公开(公告)日：2016-10-13

申请号：US15089151

申请日：2016-04-01

Applicant: STATS ChipPAC, Ltd.

Inventor： Il Kwon Shim ,  Pandi C. Marimuthu ,  Yaojian Lin

IPC: H01L23/538 ,  H01L21/48 ,  H01L25/10 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5384 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24195 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/2939 ,  H01L2224/32225 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83 ,  H01L2224/83005 ,  H01L2224/83192 ,  H01L2224/85 ,  H01L2224/85005 ,  H01L2224/92164 ,  H01L2224/92244 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/32245 ,  H01L2224/48247

Abstract: A semiconductor device comprises a first conductive layer formed on a carrier over an insulating layer. A portion of the insulating layer is removed prior to forming the first conductive layer. A first semiconductor die is disposed over the first conductive layer. A discrete electrical component is disposed over the first conductive layer adjacent to the first semiconductor die. A first encapsulant is deposited over the first conductive layer and first semiconductor layer. A conductive pillar is formed through the first encapsulant between the first conductive layer and second conductive layer. A second encapsulant is deposited around the first encapsulant, first conductive layer, and first semiconductor die. A second conductive layer is formed over the first semiconductor die, first encapsulant, and second encapsulant opposite the first conductive layer. The carrier is removed after forming the second conductive layer. A semiconductor package is mounted to the first conductive layer.

Abstract translation: 半导体器件包括在绝缘层上形成在载体上的第一导电层。 在形成第一导电层之前去除绝缘层的一部分。 第一半导体管芯设置在第一导电层上。 离散的电子部件布置在与第一半导体管芯相邻的第一导电层上。 第一密封剂沉积在第一导电层和第一半导体层上。 在第一导电层和第二导电层之间通过第一密封剂形成导电柱。 围绕第一密封剂，第一导电层和第一半导体管芯沉积第二密封剂。 在第一半导体管芯，第一密封剂和与第一导电层相对的第二密封剂之上形成第二导电层。 在形成第二导电层之后移除载体。 半导体封装被安装到第一导电层。

公开(公告)号：US09202769B2

公开(公告)日：2015-12-01

申请号：US14509785

申请日：2014-10-08

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Pandi C. Marimuthu ,  Il Kwon Shim

IPC: H01L21/44 ,  H01L23/367 ,  H01L23/00 ,  H01L23/16 ,  H01L23/31 ,  H01L21/56 ,  H01L23/552 ,  H01L21/683 ,  H01L23/538 ,  H01L23/42 ,  H01L23/498

CPC classification number: H01L23/367 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/16 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/42 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/24195 ,  H01L2224/73267 ,  H01L2224/9222 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/19 ,  H01L2924/00012

Abstract: A semiconductor device has a first semiconductor die and an encapsulant deposited over the first semiconductor die. An interconnect structure is formed over the first semiconductor die and encapsulant. A thermal interface material is formed over the first semiconductor die and encapsulant. A stiffening layer is formed over the first semiconductor die and an edge portion of the encapsulant. Alternatively, an insulating layer is formed adjacent to the first semiconductor die and a stiffening layer is formed over the insulating layer. The stiffening layer includes metal, ferrite, ceramic, or semiconductor material. A heat spreader is disposed over the first semiconductor die and a central portion of the encapsulant. Openings are formed in the heat spreader. A recess is formed in the heat spreader along an edge of the heat spreader. A coefficient of thermal expansion (CTE) of the stiffening layer is less than a CTE of the heat spreader.

Abstract translation: 半导体器件具有沉积在第一半导体管芯上的第一半导体管芯和密封剂。 在第一半导体管芯和密封剂上形成互连结构。 在第一半导体管芯和密封剂上形成热界面材料。 在第一半导体管芯上形成加强层和密封剂的边缘部分。 或者，与第一半导体管芯相邻地形成绝缘层，并且在绝缘层上形成加强层。 加强层包括金属，铁氧体，陶瓷或半导体材料。 散热器设置在第一半导体管芯上方和密封剂的中心部分。 开口形成在散热器中。 散热器沿着散热器的边缘形成凹部。 加强层的热膨胀系数（CTE）小于散热器的CTE。

公开(公告)号：US09153544B2

公开(公告)日：2015-10-06

申请号：US14194691

申请日：2014-03-01

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  Jose A. Caparas ,  Pandi C. Marimuthu

IPC: H01L23/60 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/683 ,  H01L23/498 ,  H01L23/552 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/60 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/03

Abstract: A semiconductor wafer has a plurality of semiconductor die separated by a saw street. The wafer is mounted to dicing tape. The wafer is singulated through the saw street to expose side surfaces of the semiconductor die. An ESD protection layer is formed over the semiconductor die and around the exposed side surfaces of the semiconductor die. The ESD protection layer can be a metal layer, encapsulant film, conductive polymer, conductive ink, or insulating layer covered by a metal layer. The ESD protection layer is singulated between the semiconductor die. The semiconductor die covered by the ESD protection layer are mounted to a temporary carrier. An encapsulant is deposited over the ESD protection layer covering the semiconductor die. The carrier is removed. An interconnect structure is formed over the semiconductor die and encapsulant. The ESD protection layer is electrically connected to the interconnect structure to provide an ESD path.

Abstract translation: 半导体晶片具有由锯条隔开的多个半导体管芯。 晶片安装在切割胶带上。 通过锯条将晶片分割，以露出半导体管芯的侧表面。 在半导体管芯上并围绕半导体管芯的暴露的侧表面形成ESD保护层。 ESD保护层可以是由金属层覆盖的金属层，密封剂膜，导电聚合物，导电油墨或绝缘层。 ESD保护层在半导体管芯之间分离。 由ESD保护层覆盖的半导体管芯被安装到临时载体上。 密封剂沉积在覆盖半导体管芯的ESD保护层上。 载体被移除。 在半导体管芯和密封剂上形成互连结构。 ESD保护层电连接到互连结构以提供ESD路径。

公开(公告)号：US09105532B2

公开(公告)日：2015-08-11

申请号：US14503698

申请日：2014-10-01

Applicant: STATS ChipPAC, Ltd.

Inventor： Won Kyoung Choi ,  Pandi C. Marimuthu

IPC: H01L23/485 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/13 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/05 ,  H01L24/10 ,  H01L24/11 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/11 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11822 ,  H01L2224/11906 ,  H01L2224/13 ,  H01L2224/13007 ,  H01L2224/13017 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/81191 ,  H01L2224/81201 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device has a semiconductor die with a first conductive layer formed over the die. A first insulating layer is formed over the die with a first opening in the first insulating layer disposed over the first conductive layer. A second conductive layer is formed over the first insulating layer and into the first opening over the first conductive layer. An interconnect structure is constructed by forming a second insulating layer over the first insulating layer with a second opening having a width less than the first opening and depositing a conductive material into the second opening. The interconnect structure can be a conductive pillar or conductive pad. The interconnect structure has a width less than a width of the first opening. The second conductive layer over the first insulating layer outside the first opening is removed while leaving the second conductive layer under the interconnect structure.

Abstract translation: 半导体器件具有半导体管芯，其具有形成在管芯上的第一导电层。 第一绝缘层形成在管芯上方，第一绝缘层中的第一开口布置在第一导电层上。 在第一绝缘层上形成第二导电层，并在第一导电层上形成第一导电层。 通过在第一绝缘层上形成第二绝缘层，其宽度小于第一开口的第二开口并将导电材料沉积到第二开口中来构造互连结构。 互连结构可以是导电柱或导电垫。 互连结构的宽度小于第一开口的宽度。 除去第一开口外部的第一绝缘层上的第二导电层，同时将第二导电层留在互连结构下。

公开(公告)号：US09087930B2

公开(公告)日：2015-07-21

申请号：US14274599

申请日：2014-05-09

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen ,  Hin Hwa Goh ,  Yu Gu ,  Il Kwon Shim ,  Rui Huang ,  Seng Guan Chow ,  Jianmin Fang ,  Xia Feng

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L23/3114 ,  H01L21/31 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/522 ,  H01L23/528 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01043 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10156 ,  H01L2924/10157 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2224/19 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/00012 ,  H01L2224/214

Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.

Abstract translation: 半导体器件具有形成在半导体管芯的表面上的半导体管芯和导电层。 可以在半导体管芯中形成第一通道。 密封剂沉积在半导体管芯上。 可以在密封剂中形成第二通道。 在半导体管芯和第一导电层上形成第一绝缘层并进入第一沟道。 第一绝缘层延伸到第二通道中。 第一绝缘层的拉伸强度大于150MPa，伸长率在35-150％之间，厚度为2-30微米。 在形成第一绝缘层之前，可以在半导体管芯上方形成第二绝缘层。 在半导体管芯和密封剂上形成互连结构。 互连结构电连接到第一导电层。 第一绝缘层在形成互连结构期间提供应力释放。

公开(公告)号：US20150061123A1

公开(公告)日：2015-03-05

申请号：US14512614

申请日：2014-10-13

Applicant: STATS CHIPPAC, LTD.

Inventor： Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen

IPC: H01L23/00 ,  H01L23/31

CPC classification number: H01L24/14 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/291 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0348 ,  H01L2224/0361 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05557 ,  H01L2224/05567 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13008 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/20101 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00012

Abstract: A semiconductor device has a semiconductor die with an encapsulant deposited over the semiconductor die. A first insulating layer having high tensile strength and elongation is formed over the semiconductor die and encapsulant. A first portion of the first insulating layer is removed by a first laser direct ablation to form a plurality of openings in the first insulating layer. The openings extend partially through the first insulating layer or into the encapsulant. A second portion of the first insulating layer is removed by a second laser direct ablation to form a plurality of trenches in the first insulating layer. A conductive layer is formed in the openings and trenches of the first insulating layer. A second insulating layer is formed over the conductive layer. A portion of the second insulating layer is removed by a third laser direct ablation. Bumps are formed over the conductive layer.

Abstract translation: 半导体器件具有沉积在半导体管芯上的具有密封剂的半导体管芯。 在半导体管芯和密封剂上形成具有高拉伸强度和伸长率的第一绝缘层。 通过第一激光直接消融去除第一绝缘层的第一部分，以在第一绝缘层中形成多个开口。 这些开口部分地延伸穿过第一绝缘层或者进入密封剂。 通过第二激光直接烧蚀去除第一绝缘层的第二部分，以在第一绝缘层中形成多个沟槽。 在第一绝缘层的开口和沟槽中形成导电层。 在导电层上形成第二绝缘层。 通过第三激光直接烧蚀去除第二绝缘层的一部分。 在导电层上形成凸起。