公开(公告)号：US20060170089A1

公开(公告)日：2006-08-03

申请号：US11147451

申请日：2005-06-08

申请人： Masataka Mizukoshi

发明人： Masataka Mizukoshi

IPC分类号： H01L23/02

CPC分类号： H03H9/059 ,  H01L23/041 ,  H01L23/10 ,  H01L23/3114 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/31 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05655 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14 ,  H01L2224/1403 ,  H01L2224/16 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/8183 ,  H01L2224/83907 ,  H01L2224/83951 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00014

摘要： The electronic device comprises a first substrate 10 with an electric circuit element formed in a predetermined region of one primary surface, a second substrate 12 formed, opposed to said one primary surface of the first substrate 10, sealing portions 26, 40 formed between the first substrate 10 and the second substrate 12, enclosing the predetermined region of the first substrate 10, and an adhesion layer 42 formed on the side surfaces of the sealing parts 26, 40. The adhesion layer is formed on the side surfaces of the first sealing structure 26 on the side of the first substrate 10 and the second sealing structure 40 on the side of the second substrate 12, whereby when the first sealing structure 26 and the second sealing structure 40 are bonded to each other, the adhesion between the first sealing structure 26 and the second sealing structure 40 can be sufficiently ensured.

摘要翻译： 电子设备包括：第一基板10，其具有形成在一个主表面的预定区域中的电路元件;第二基板12，形成为与第一基板10的所述一个主表面相对;密封部分26,40，形成在第一 衬底10和包围第一衬底10的预定区域的第二衬底12以及形成在密封部分26,40的侧表面上的粘合层42。 在第一基板10侧的第一密封结构体26的侧面和第二基板12侧的第二密封结构体40上形成粘合层，由此当第一密封结构体26和第二密封结构体 40彼此接合，可以充分地确保第一密封结构26和第二密封结构40之间的粘合。

公开(公告)号：US06979644B2

公开(公告)日：2005-12-27

申请号：US10420751

申请日：2003-04-23

申请人： Koji Omote ,  Masataka Mizukoshi ,  Osamu Taniguchi

发明人： Koji Omote ,  Masataka Mizukoshi ,  Osamu Taniguchi

IPC分类号： H01L23/12 ,  H01L21/768 ,  H01L23/48 ,  H01L23/538 ,  H01L25/065 ,  H01L21/44

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/15192 ,  H01L2924/3011 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A method of manufacturing an electronic circuit component, including the steps of: (a) forming a first thin film circuit element on a surface of a circuit board made of an Si substrate; (b) forming a hole or trench from the surface of the circuit board through at least a portion of a thickness of the Si substrate by etching; (c) forming an insulating film covering a surface of the formed hole or trench; (d) adhering a dry film of photoresist to the surface of the circuit board, the dry film capping an opening of the hole or trench; (e) patterning the dry film; and (f) by using the patterned dry film as a mask, etching the insulating film. An electronic circuit component having through conductors and being less influenced by high temperature annealing can be manufactured.

摘要翻译： 一种制造电子电路部件的方法，包括以下步骤：（a）在由Si衬底制成的电路板的表面上形成第一薄膜电路元件; （b）通过蚀刻从所述电路板的表面通过所述Si衬底的厚度的至少一部分形成孔或沟槽; （c）形成覆盖所形成的孔或沟槽的表面的绝缘膜; （d）将光致抗蚀剂的干膜粘附到电路板的表面，干膜封盖孔或沟槽的开口; （e）图案化干膜; 和（f）通过使用图案化的干膜作为掩模，蚀刻绝缘膜。 可以制造具有通过导体并受较低温度退火影响的电子电路部件。

公开(公告)号：US20050109533A1

公开(公告)日：2005-05-26

申请号：US11023012

申请日：2004-12-28

申请人： Mamoru Kurashina ,  Yoshikatsu Ishizuki ,  Nawalage Cooray ,  Masataka Mizukoshi

发明人： Mamoru Kurashina ,  Yoshikatsu Ishizuki ,  Nawalage Cooray ,  Masataka Mizukoshi

IPC分类号： H05K3/00 ,  H05K3/28 ,  H05K3/46 ,  H05K1/03 ,  H05K1/11

CPC分类号： H05K3/28 ,  H05K3/0023 ,  H05K3/0082 ,  H05K3/4647 ,  H05K2201/0367 ,  H05K2201/09881 ,  H05K2203/0508

摘要： A manufacturing method of a circuit board includes the steps of: forming projecting electrodes on a substrate; forming a photosensitive resin film on the substrate so as to cover the projecting electrodes; exposing a substantially entire surface of the photosensitive film; and melting the surface of the photosensitive film so as to expose the projecting electrodes.

摘要翻译： 电路板的制造方法包括以下步骤：在基板上形成突出电极; 在基板上形成感光树脂膜以覆盖突出电极; 曝光感光膜的大致整个表面; 并且使感光膜的表面熔融以使突出电极露出。

公开(公告)号：US06896998B2

公开(公告)日：2005-05-24

申请号：US10320398

申请日：2002-12-17

申请人： Masataka Mizukoshi

发明人： Masataka Mizukoshi

IPC分类号： G03F1/68 ,  G03F1/70 ,  G03F7/20 ,  G03F9/00 ,  H01L21/027 ,  H01L21/60 ,  H01L23/538 ,  G03C5/00

CPC分类号： G03F9/7003 ,  G03F7/70291 ,  G03F7/70466 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/30107

摘要： A pattern forming method comprising the steps of: detecting a position of a base pattern formed on a substrate; forming a photosensitive resin film on the substrate; correcting a pattern data of a pattern to be formed on the substrate, based on a positional information of the base pattern to thereby compute a corrected pattern data; displaying a mask pattern on a liquid crystal panel, based on the corrected pattern data; and exposing the photosensitive resin film with the liquid crystal panel as a mask and developing the same to thereby pattern the photosensitive resin film. Even when a base pattern has rotations, shrinkages, distortions, etc., a prescribed upper layer pattern can be formed in alignment with the lower layer pattern.

摘要翻译： 一种图案形成方法，包括以下步骤：检测形成在基底上的基底图案的位置; 在基板上形成感光性树脂膜; 基于所述基本图案的位置信息来校正要在所述基板上形成的图案的图案数据，从而计算校正图案数据; 基于校正的图案数据在液晶面板上显示掩模图案; 并将作为掩模的液晶面板的感光性树脂膜曝光并使其显影，从而对感光性树脂膜进行图案化。 即使当基底图案具有旋转，收缩，变形等时，也可以形成与下层图案对准的规定的上层图案。

公开(公告)号：US06580169B2

公开(公告)日：2003-06-17

申请号：US10191533

申请日：2002-07-10

申请人： Seiki Sakuyama ,  Yasuo Yamagishi ,  Masataka Mizukoshi

发明人： Seiki Sakuyama ,  Yasuo Yamagishi ,  Masataka Mizukoshi

IPC分类号： H01L2348

CPC分类号： H05K3/3484 ,  H01L21/4853 ,  H01L21/6835 ,  H01L23/49883 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11003 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/141 ,  H01L2224/16145 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1532 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/0266 ,  H05K2201/10477 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2203/043 ,  H05K2203/0568 ,  H05K2203/0574 ,  H05K2203/0577 ,  H05K2203/0769

摘要： The present invention relates to a method for forming bumps on a substrate provided with electrode pads. The method includes providing a mask having openings corresponding to the electrode pads, filling each of the openings with a solder paste, and heat treating the solder paste, wherein the solder paste includes solder powder. Preferably, the solder powder contains no more than 10 wt % of particles whose diameter is greater than the thickness of the mask and no more than 1.5 times this thickness. Preferably, the solder powder contains no more than 10 wt % of particles whose diameter is not less than 40% the diameter of the opening portions, or no less than 30 wt % of particles whose diameter is 40 to 100% the thickness of the mask.

公开(公告)号：US06344407B1

公开(公告)日：2002-02-05

申请号：US09691075

申请日：2000-10-19

申请人： Hirohisa Matsuki ,  Fumihiko Taniguchi ,  Kunio Kodama ,  Eiji Watanabe ,  Masataka Mizukoshi ,  Hiroyuki Matsui

发明人： Hirohisa Matsuki ,  Fumihiko Taniguchi ,  Kunio Kodama ,  Eiji Watanabe ,  Masataka Mizukoshi ,  Hiroyuki Matsui

IPC分类号： B23K3522

CPC分类号： B23K35/38 ,  B23K35/262 ,  B23K35/268 ,  B23K35/3618 ,  B23K2101/40 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/11 ,  H01L2224/11334 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01054 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/15787 ,  H05K3/3489 ,  H01L2924/00 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2224/05166

摘要： A semiconductor device manufacturing method comprises the steps of forming solder bumps on an underlying metal film of a semiconductor device, and placing the semiconductor device and the solder layer in a reduced pressure atmosphere containing formic acid to form the solder bumps. Accordingly, the solder bumps can be formed without flux generating voids in the solder layer. Furthermore, the cleaning required after the solder bumps are formed can be omitted.

摘要翻译： 半导体器件制造方法包括以下步骤：在半导体器件的下面的金属膜上形成焊料凸块，并将半导体器件和焊料层放置在含有甲酸的减压气氛中以形成焊料凸块。 因此，可以在焊料层中形成焊剂凸块而没有焊剂产生空隙。 此外，可以省略在形成焊料凸块之后所需的清洁。

公开(公告)号：US06319810B1

公开(公告)日：2001-11-20

申请号：US08659356

申请日：1996-06-06

申请人： Masayuki Ochiai ,  Yasuo Yamagishi ,  Ichiro Yamaguchi ,  Masahiro Yoshikawa ,  Koki Otake ,  Masataka Mizukoshi ,  Yuuji Watanabe

发明人： Masayuki Ochiai ,  Yasuo Yamagishi ,  Ichiro Yamaguchi ,  Masahiro Yoshikawa ,  Koki Otake ,  Masataka Mizukoshi ,  Yuuji Watanabe

IPC分类号： H01L2144

CPC分类号： H01L24/12 ,  B23K3/0623 ,  H01L21/4853 ,  H01L21/6835 ,  H01L24/11 ,  H01L2224/11003 ,  H01L2224/1111 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H05K3/3463 ,  H05K3/3478 ,  H05K3/3484 ,  H05K3/3489 ,  H05K2201/10992 ,  H05K2203/0113 ,  H05K2203/016 ,  H05K2203/0278 ,  H05K2203/0338 ,  H05K2203/041 ,  H05K2203/043 ,  H05K2203/0557 ,  H05K2203/087 ,  H05K2203/1105 ,  H05K2203/1157 ,  H05K2203/1476 ,  H01L2924/00 ,  H01L2224/48

摘要： Method for forming solder bumps on a first member such as a semiconductor chip having electrode pads formed thereon. A flat plate having holes is prepared and the holes are filled with solder paste by squeezing. The flat plate is then overlapped with the first member with the flat plate above the first plate. The flat plate and the first member are heated to a temperature higher than the melting point of the solder alloy in the solder paste. Therefore, solder bumps having identical sizes and uniform structures can be obtained.

摘要翻译： 在诸如其上形成有电极焊盘的半导体芯片的第一部件上形成焊料凸块的方法。 准备具有孔的平板，并通过挤压填充焊膏。 然后平板与第一构件重叠，平板在第一板上。 平板和第一构件被加热到高于焊膏中的焊料合金的熔点的温度。 因此，可以获得具有相同尺寸和均匀结构的焊料凸块。

公开(公告)号：US6088233A

公开(公告)日：2000-07-11

申请号：US195232

申请日：1998-11-18

申请人： Makoto Iijima ,  Tetsushi Wakabayashi ,  Toshio Hamano ,  Masaharu Minamizawa ,  Masashi Takenaka ,  Taturou Yamashita ,  Masataka Mizukoshi

发明人： Makoto Iijima ,  Tetsushi Wakabayashi ,  Toshio Hamano ,  Masaharu Minamizawa ,  Masashi Takenaka ,  Taturou Yamashita ,  Masataka Mizukoshi

IPC分类号： H01L23/12 ,  H01L21/48 ,  H01L21/60 ,  H01L23/10 ,  H01L23/14 ,  H01L23/24 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18 ,  H05K3/46 ,  H05K7/02

CPC分类号： H01L24/81 ,  H01L21/486 ,  H01L23/10 ,  H01L23/142 ,  H01L23/24 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H05K3/4602 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/16151 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3025 ,  H05K2201/0959 ,  H05K2201/09672

摘要： A semiconductor device includes a board base having through-holes filled with a filling core, an additive layer provided on an upper surface of the board base as well as an upper surface of the filling core wherein the additive layer includes a wiring pattern having one or more paths, a semiconductor chip fixed on an upper surface of the additive layer, and nodes provided on a lower surface of the board base, wherein the one or more paths are laid out without a restriction posed by the through-holes, and are used for electrically connecting the semiconductor chip and the nodes.

摘要翻译： 半导体器件包括具有填充有填充芯的通孔的板基板，设置在基板的上表面上的添加层以及填充芯的上表面，其中添加层包括布线图案，该布线图案具有一个或 更多路径，固定在所述添加层的上表面上的半导体芯片，以及设置在所述基板的下表面上的节点，其中所述一个或多个路径被布置而不受所述通孔所构成的限制，并且被使用 用于电连接半导体芯片和节点。

公开(公告)号：US6063640A

公开(公告)日：2000-05-16

申请号：US30349

申请日：1998-02-25

申请人： Masataka Mizukoshi ,  Hidehiko Akasaki ,  Masao Nakano ,  Yasuhiro Fujii ,  Shinnosuke Kamata ,  Makoto Yanagisawa ,  Yasurou Matsuzaki ,  Toyonobu Yamada ,  Masami Matsuoka ,  Hiroyoshi Tomita

发明人： Masataka Mizukoshi ,  Hidehiko Akasaki ,  Masao Nakano ,  Yasuhiro Fujii ,  Shinnosuke Kamata ,  Makoto Yanagisawa ,  Yasurou Matsuzaki ,  Toyonobu Yamada ,  Masami Matsuoka ,  Hiroyoshi Tomita

IPC分类号： H01L23/58 ,  G01R31/26 ,  H01L21/66

CPC分类号： H01L22/32 ,  H01L22/22 ,  H01L2224/05554 ,  Y10S438/977

摘要： A semiconductor wafer testing method includes a pre-test step for forming a temporary test film on a surface of a semiconductor wafer, a test step for testing the semiconductor wafer by applying a probe to the temporary test film and a post-test step for exfoliating the temporary test film from the surface of the semiconductor wafer. The temporary test film includes test electrode groups each provided with a plurality of regularly arranged test electrodes, and wiring patterns for electrically connecting the test electrodes with corresponding ones of semiconductor unit electrodes in respective semiconductor units on the semiconductor wafer. Probe pins of said probe are arranged so as to be aligned with corresponding ones of the test electrodes of the respective test electrode groups.

摘要翻译： 半导体晶片测试方法包括：在半导体晶片的表面上形成临时测试膜的预测试步骤，通过向临时测试膜施加探针来测试半导体晶片的测试步骤和用于去角质的后测试步骤 来自半导体晶片表面的临时测试膜。 临时测试膜包括各自设置有多个规则排列的测试电极的测试电极组和用于将测试电极与半导体晶片上的各个半导体单元中的相应半导体单元电极电连接的布线图案。 所述探针的探头针布置成与各个测试电极组的相应测试电极对齐。

公开(公告)号：US5521435A

公开(公告)日：1996-05-28

申请号：US301403

申请日：1994-09-08

申请人： Masataka Mizukoshi

发明人： Masataka Mizukoshi

IPC分类号： H01L23/12 ,  H01L21/60 ,  H01L23/24 ,  H01L23/498 ,  H01L23/538 ,  H01L23/04

CPC分类号： H01L24/81 ,  H01L23/24 ,  H01L23/49816 ,  H01L23/49833 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15173 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/351 ,  Y10T29/49144 ,  Y10T29/49146

摘要： A semiconductor device includes a package substrate and a semiconductor chip provided on the package substrate, wherein there is provided a jumper substrate carrying thereon electrodes and conductor patterns that connect the electrodes, such that the jumper substrate is mounted upon the package substrate for providing an interconnection between the electrode patterns provided on the upper major surface of the package substrate in electrical connection with the electrode pads on the semiconductor chip and the electrodes that are isolated in correspondence to the through-holes provided on the package substrate.