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51.发明申请INTEGRATED CIRCUIT STRUCTURE INCORPORATING A CONDUCTOR LAYER WITH BOTH TOP SURFACE AND SIDEWALL PASSIVATION AND A METHOD OF FORMING THE INTEGRATED CIRCUIT STRUCTURE 有权集成电路结构，包含两个顶表面和侧壁钝化的导体层，以及形成集成电路结构的方法公开(公告)号：US20120025383A1
公开(公告)日：2012-02-02
申请号：US12845065
申请日：2010-07-28
申请人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Timothy D. Sullivan
发明人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Timothy D. Sullivan
IPC分类号： H01L23/485 , H01L21/768
CPC分类号： H01L21/76885 , H01L21/76852 , H01L23/3114 , H01L23/525 , H01L23/53238 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0231 , H01L2224/02331 , H01L2224/03462 , H01L2224/0401 , H01L2224/05007 , H01L2224/05008 , H01L2224/05027 , H01L2224/05082 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05169 , H01L2224/05171 , H01L2224/05572 , H01L2224/05644 , H01L2224/05647 , H01L2224/13022 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13118 , H01L2224/1312 , H01L2224/13139 , H01L2224/13147 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/1305 , H01L2924/14 , H01L2924/00 , H01L2224/05552
摘要： Disclosed are embodiments of a structure having a metal layer with top surface and sidewall passivation and a method of forming the structure. In one embodiment, a metal layer is electroplated onto a portion of a seed layer at the bottom of a trench. Then, the sidewalls of the metal layer are exposed and, for passivation, a second metal layer is electroplated onto the top surface and sidewalls of the metal layer. In another embodiment, a trench is formed in a dielectric layer. A seed layer is formed over the dielectric layer, lining the trench. A metal layer is electroplated onto the portion of the seed layer within the trench and a second metal layer is electroplated onto the top surface of the metal layer. Thus, in this case, passivation of the top surface and sidewalls of the metal layer is provided by the second metal layer and the dielectric layer, respectively.
摘要翻译： 公开了具有具有顶表面和侧壁钝化的金属层的结构的实施例以及形成该结构的方法。 在一个实施例中，金属层电镀在沟槽底部的种子层的一部分上。 然后，暴露金属层的侧壁，为了钝化，将第二金属层电镀在金属层的顶表面和侧壁上。 在另一个实施例中，在电介质层中形成沟槽。 在电介质层上形成种子层，衬在沟槽上。 将金属层电镀在沟槽内的种子层的部分上，并且将第二金属层电镀到金属层的顶表面上。 因此，在这种情况下，金属层的顶表面和侧壁的钝化分别由第二金属层和电介质层提供。
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52.发明申请Solder Interconnect with Non-Wettable Sidewall Pillars and Methods of Manufacture 有权焊接与不可湿润的侧壁支柱和制造方法互连公开(公告)号：US20110193218A1
公开(公告)日：2011-08-11
申请号：US12700863
申请日：2010-02-05
申请人： Charles L. Arvin , Raschid J. Bezama , Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , David L. Questad , Wolfgang Sauter , Timothy D. Sullivan , Brian R. Sundlof
发明人： Charles L. Arvin , Raschid J. Bezama , Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , David L. Questad , Wolfgang Sauter , Timothy D. Sullivan , Brian R. Sundlof
IPC分类号： H01L23/498 , H01L21/768
CPC分类号： H01L24/13 , H01L23/49811 , H01L24/11 , H01L24/16 , H01L2224/0401 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/10126 , H01L2224/11334 , H01L2224/1146 , H01L2224/1147 , H01L2224/1182 , H01L2224/119 , H01L2224/13017 , H01L2224/13018 , H01L2224/1308 , H01L2224/13083 , H01L2224/13084 , H01L2224/13101 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13565 , H01L2224/1357 , H01L2224/13687 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/3841 , H01L2924/00014 , H01L2924/01024 , H01L2924/01026 , H01L2924/01032 , H01L2924/00012 , H01L2924/00
摘要： A solder interconnect structure is provided with non-wettable sidewalls and methods of manufacturing the same. The method includes forming a nickel or nickel alloy pillar on an underlying surface. The method further includes modifying the sidewall of the nickel or nickel alloy pillar to prevent solder wetting on the sidewall.
摘要翻译： 焊接互连结构设置有不可润湿的侧壁及其制造方法。 该方法包括在下面的表面上形成镍或镍合金支柱。 该方法还包括修改镍或镍合金柱的侧壁以防止在侧壁上的焊料润湿。
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公开(公告)号：US07843069B2
公开(公告)日：2010-11-30
申请号：US11849409
申请日：2007-09-04
IPC分类号： H01L23/49
CPC分类号： H01L24/03 , H01L2224/05001 , H01L2224/05073 , H01L2224/05553 , H01L2224/05624 , H01L2224/05647 , H01L2224/05681 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/00014
摘要： A wire bond pad and method of fabricating the wire bond pad. The method including: providing a substrate; forming an electrically conductive layer on a top surface of the substrate; patterning the conductive layer into a plurality of wire bond pads spaced apart; and forming a protective dielectric layer on the top surface of the substrate in spaces between adjacent wire bond pads, top surfaces of the dielectric layer in the spaces coplanar with coplanar top surfaces of the wire bond pads.
摘要翻译： 引线接合焊盘和制造引线接合焊盘的方法。 该方法包括：提供衬底; 在所述基板的顶表面上形成导电层; 将导电层图案化成间隔开的多个引线接合焊盘; 以及在相邻引线接合焊盘之间的空间中在基板的顶表面上形成保护电介质层，在与键合焊盘的共面顶表面共面的空间中的电介质层的顶表面。
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公开(公告)号：US07682961B2
公开(公告)日：2010-03-23
申请号：US11422979
申请日：2006-06-08
IPC分类号： H01L21/44
CPC分类号： H01L24/11 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/0345 , H01L2224/03462 , H01L2224/0347 , H01L2224/0361 , H01L2224/03912 , H01L2224/03914 , H01L2224/0401 , H01L2224/05027 , H01L2224/05073 , H01L2224/05166 , H01L2224/05184 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/11334 , H01L2224/1147 , H01L2224/11849 , H01L2224/11912 , H01L2224/13006 , H01L2224/131 , H01L2924/00013 , H01L2924/0002 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/04953 , H01L2924/05042 , H01L2924/181 , H01L2924/00014 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552 , H01L2924/00
摘要： In a first aspect, a method comprises depositing a first metal containing layer into a trench structure, which contacts a metalized area of a semiconductor structure. The method further includes patterning at least one opening in a resist to the first metal containing layer. The opening should be in alignment with the trench structure. At least a pad metal containing layer is formed within the at least one opening (preferably by electroplating processes). The resist and the first metal layer underlying the resist are then etched (with the second metal layer acting as a mask, in embodiments). The method includes flowing solder material within the trench and on pad metal containing layer after the etching process. The structure is a controlled collapse chip connection (C4) structure comprising at least one electroplated metal layer formed in a resist pattern to form at least one ball limiting metallurgical layer. The structure further includes an underlying metal layer devoid of undercuts.
摘要翻译： 在第一方面，一种方法包括将第一含金属层沉积到与半导体结构的金属化区域接触的沟槽结构中。 该方法还包括将抗蚀剂中的至少一个开口图案化为第一含金属层。 开口应与沟槽结构对齐。 在至少一个开口内（优选通过电镀工艺）形成至少一垫层金属层。 然后蚀刻抗蚀剂和抗蚀剂下面的第一金属层（在实施例中第二金属层用作掩模）。 该方法包括在蚀刻工艺之后使沟槽内的焊料材料和含焊垫金属的层流动。 该结构是受控的崩溃芯片连接（C4）结构，包括至少一个以抗蚀剂图案形成的电镀金属层，以形成至少一个球限制冶金层。 该结构还包括没有底切的底层金属层。
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公开(公告)号：US07411135B2
公开(公告)日：2008-08-12
申请号：US10711885
申请日：2004-10-12
IPC分类号： H01R12/04
CPC分类号： H01L23/544 , H01L22/24 , H01L22/32 , H01L22/34 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/48 , H01L2223/5448 , H01L2224/02166 , H01L2224/0392 , H01L2224/0401 , H01L2224/04042 , H01L2224/05181 , H01L2224/05624 , H01L2224/05666 , H01L2224/05681 , H01L2224/13099 , H01L2224/48463 , H01L2224/85399 , H01L2924/00014 , H01L2924/01013 , H01L2924/01022 , H01L2924/01033 , H01L2924/01073 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , Y10T29/49155 , Y10T29/49165 , Y10T29/49204 , Y10T29/49227 , H01L2224/45099
摘要： An integrated circuit has a wiring layer below an insulator layer. A pad comprises a conductive material that is on the insulator layer. The pad has a wirebond connection region and a probe pad region. An inspection mark is between the wirebond connection region and the probe pad region. The inspection mark comprises an opening in the insulator layer that is filled with the conductive material. In addition, a contact that is through the insulator layer is adapted to electrically connect the conductor wire in the wiring layer to the pad. The contact is formed of the same conductive material used for the pad and the inspection mark.
摘要翻译： 集成电路在绝缘体层下方具有布线层。 衬垫包括位于绝缘体层上的导电材料。 焊盘具有引线连接区域和探针焊盘区域。 导线连接区域和探针焊盘区域之间的检查标记。 检查标记包括填充有导电材料的绝缘体层中的开口。 此外，穿过绝缘体层的接触件适于将布线层中的导线电连接到焊盘。 接触由用于垫和检查标记的相同的导电材料形成。
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56.发明授权Prevention of backside cracks in semiconductor chips or wafers using backside film or backside wet etch 有权使用背面薄膜或背面湿蚀刻防止半导体芯片或晶片的背面裂缝公开(公告)号：US07405139B2
公开(公告)日：2008-07-29
申请号：US11462124
申请日：2006-08-03
申请人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Jerome B. Lasky , Christopher D. Muzzy , Wolfgang Sauter
发明人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Jerome B. Lasky , Christopher D. Muzzy , Wolfgang Sauter
IPC分类号： H01L21/322
CPC分类号： H01L29/34 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/10253 , H01L2924/15174 , H01L2924/15311 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A method of preventing the formation of cracks on the backside of a silicon (Si) semiconductor chip or wafer during the processing thereof. Also provided is a method for inhibiting the propagation of cracks, which have already formed in the backside of a silicon chip during the processing thereof and prior to the joining thereto of a substrate during the fabrication of an electronic package. The methods entail either treating the backside with a wet etch, or alternatively, applying a protective film layer thereon prior to forming an electronic package incorporating the chip or wafer.
摘要翻译： 一种防止在硅（Si）半导体芯片或晶片的后侧形成裂纹的方法。 还提供了一种在电子封装的制造期间，在处理之前和在与基板接合之前，已经形成在硅芯片背面的裂纹扩散的方法。 该方法需要用湿蚀刻处理背面，或者在形成包含芯片或晶片的电子封装之前，在其上施加保护膜层。
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57.发明申请PREVENTION OF BACKSIDE CRACKS IN SEMICONDUCTOR CHIPS OR WAFERS USING BACKSIDE FILM OR BACKSIDE WET ETCH 有权使用背面胶片或背面浸湿剂防止半导体芯片或波纹中的背面裂纹公开(公告)号：US20080122037A1
公开(公告)日：2008-05-29
申请号：US11462124
申请日：2006-08-03
申请人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Jerome B. Lasky , Christopher D. Muzzy , Wolfgang Sauter
发明人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Jerome B. Lasky , Christopher D. Muzzy , Wolfgang Sauter
CPC分类号： H01L29/34 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/10253 , H01L2924/15174 , H01L2924/15311 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A method of preventing the formation of cracks on the backside of a silicon (Si) semiconductor chip or wafer during the processing thereof. Also provided is a method for inhibiting the propagation of cracks, which have already formed in the backside of a silicon chip during the processing thereof and prior to the joining thereto of a substrate during the fabrication of an electronic package. The methods entail either treating the backside with a wet etch, or alternatively, applying a protective film layer thereon prior to forming an electronic package incorporating the chip or wafer.
摘要翻译： 一种防止在硅（Si）半导体芯片或晶片的后侧形成裂纹的方法。 还提供了一种在电子封装的制造期间，在处理之前和在与基板接合之前，已经形成在硅芯片背面的裂纹扩散的方法。 该方法需要用湿蚀刻处理背面，或者在形成包含芯片或晶片的电子封装之前，在其上施加保护膜层。
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公开(公告)号：US20080099877A1
公开(公告)日：2008-05-01
申请号：US11553176
申请日：2006-10-26
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/5258 , H01L23/5254 , H01L23/5256 , H01L23/562 , H01L2924/0002 , H01L2924/00
摘要： A conductor-filled damage propagation barrier is formed extending into a low-k dielectric layer between a fuse and an adjacent circuit element for preventing propagation of damage during a fuse blow operation. Conductor material filling the damage propagation barrier is formed from the same conductor layer as that used to form an interconnect structure.
摘要翻译： 导体填充的损伤传播屏障形成为延伸到保险丝和相邻电路元件之间的低k电介质层，以防止在保险丝熔断操作期间传播损坏。 填充损伤传播屏障的导体材料由与用于形成互连结构的导体层相同的导体层形成。
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59.发明授权Structures and methods for improving solder bump connections in semiconductor devices 有权用于改善半导体器件中的焊料凸点连接的结构和方法公开(公告)号：US08916464B2
公开(公告)日：2014-12-23
申请号：US12344711
申请日：2008-12-29
申请人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Timothy D. Sullivan
发明人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Timothy D. Sullivan
IPC分类号： H01L23/488 , H01L21/44 , H01L23/00
CPC分类号： H01L24/13 , H01L24/03 , H01L24/05 , H01L2224/0345 , H01L2224/03452 , H01L2224/0401 , H01L2224/05011 , H01L2224/05017 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05551 , H01L2224/05555 , H01L2224/05557 , H01L2224/05644 , H01L2224/13006 , H01L2224/13022 , H01L2224/13025 , H01L2224/13111 , H01L2224/16225 , H01L2224/16227 , H01L2924/00013 , H01L2924/01002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/0102 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01093 , H01L2924/0132 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2924/0103 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599
摘要： Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a via formed in a dielectric layer to expose a contact pad and a capture pad formed in the via and over the dielectric layer. The capture pad has openings over the dielectric layer to form segmented features. The solder bump is deposited on the capture pad and the openings over the dielectric layer.
摘要翻译： 具有改善的焊料凸点连接的结构和制造这种结构的方法在本文中提供。 该结构包括在电介质层中形成的通孔，以露出形成在通孔中和电介质层上的接触焊盘和捕获焊盘。 捕获垫在电介质层上具有开口以形成分段特征。 焊料凸块沉积在捕获垫上并且在介电层上沉积开口。
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60.发明授权Pad cushion structure and method of fabrication for Pb-free C4 integrated circuit chip joining 有权无衬垫C4集成电路芯片接合的垫垫结构及其制造方法公开(公告)号：US08809182B2
公开(公告)日：2014-08-19
申请号：US12113230
申请日：2008-05-01
IPC分类号： H01L21/44
CPC分类号： H01L24/11 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/14 , H01L2224/02125 , H01L2224/0231 , H01L2224/0236 , H01L2224/024 , H01L2224/0401 , H01L2224/04042 , H01L2224/05569 , H01L2224/05624 , H01L2224/05647 , H01L2224/13022 , H01L2224/13099 , H01L2224/13111 , H01L2224/16 , H01L2224/45124 , H01L2224/48724 , H01L2224/48747 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01076 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/30107 , H01L2924/00014 , H01L2924/00
摘要： A controlled collapse chip connection (C4) method and integrated circuit structure for lead (Pb)-free solder balls with stress relief to the underlying insulating layers of the integrated circuit chip by disposing soft thick insulating cushions beneath the solder balls and connecting the metallization of the integrated circuit out-of-contact of the cushions but within the pitch of the solder balls.
摘要翻译： 一种控制崩溃芯片连接（C4）方法和用于无铅焊料球的集成电路结构，其通过在焊球下方设置柔软的厚绝缘垫并将金属化连接到集成电路芯片的下层绝缘层 衬垫的集成电路不接触，但在焊球的间距内。
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