公开(公告)号：US20150061102A1

公开(公告)日：2015-03-05

申请号：US14470159

申请日：2014-08-27

Applicant: XINTEC INC.

Inventor： Chia-Sheng LIN ,  Yen-Shih HO ,  Tsang-Yu LIU

IPC: H01L23/00 ,  H01L21/02 ,  H01L23/48

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/3114 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L27/14618 ,  H01L27/14683 ,  H01L27/1469 ,  H01L31/02005 ,  H01L2224/02372 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05583 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2924/1204 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: An electronic device package and fabrication method thereof is provided. First, a semiconductor substrate is provided and the upper surface of it is etched to from recesses. A first isolation layer is formed on the upper surface and the sidewalls of the recesses. A conductive part is formed to fulfill the recesses and a conductive pad is formed on the first isolation layer to connect the conductive part. An electronic device is combined with the semiconductor substrate on the supper surface, wherein the electronic device has a connecting pad electrically connected to the conductive pad. The semiconductor substrate is thinned form its lower surface to expose the conductive part. A second isolation layer is formed below the lower surface and has an opening to expose the conductive part. A redistribution metal line is formed below the second isolation layer and in the opening to electrically connect to the conductive part.

Abstract translation: 提供了一种电子器件封装及其制造方法。 首先，提供半导体衬底，并且从凹部蚀刻其上表面。 第一隔离层形成在凹槽的上表面和侧壁上。 形成导电部件以实现凹部，并且在第一隔离层上形成导电焊盘以连接导电部件。 电子设备与晚餐表面上的半导体衬底组合，其中电子设备具有电连接到导电焊盘的连接焊盘。 半导体衬底从其下表面变薄以暴露导电部件。 第二隔离层形成在下表面下方并具有用于暴露导电部分的开口。 在第二隔离层下方和开口中形成再分布金属线，以电连接到导电部分。

公开(公告)号：US20140332968A1

公开(公告)日：2014-11-13

申请号：US14339323

申请日：2014-07-23

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Shu-Ming CHANG ,  Yu-Lung HUANG ,  Chao-Yen LIN ,  Wei-Luen SUEN ,  Chien-Hui CHEN

IPC: H01L23/498

CPC classification number: H01L23/49805 ,  G06K9/00006 ,  G06K9/00053 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/02381 ,  H01L2224/024 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48669 ,  H01L2224/48687 ,  H01L2224/4869 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A chip package is provided. The chip package includes a chip having an upper surface, a lower surface and a sidewall. The chip includes a sensing region or device region and a signal pad region adjacent to the upper surface. A shallow recess structure is located outside of the signal pad region and extends from the upper surface toward the lower surface along the sidewall. The shallow recess structure has at least a first recess and a second recess under the first recess. A redistribution layer is electrically connected to the signal pad region and extends into the shallow recess structure. A first end of a wire is located in the shallow recess structure and is electrically connected to the redistribution layer. A second end of the wire is used for external electrical connection. A method for forming the chip package is also provided.

Abstract translation: 提供芯片封装。 芯片封装包括具有上表面，下表面和侧壁的芯片。 芯片包括感测区域或器件区域以及与上表面相邻的信号焊盘区域。 浅凹陷结构位于信号垫区域的外侧，并且沿着侧壁从上表面向下表面延伸。 浅凹部结构在第一凹部下方具有至少第一凹部和第二凹部。 再分配层电连接到信号焊盘区域并延伸到浅凹陷结构中。 电线的第一端位于浅凹陷结构中，并且电连接到再分配层。 电线的第二端用于外部电气连接。 还提供了一种用于形成芯片封装的方法。

公开(公告)号：US20140225276A1

公开(公告)日：2014-08-14

申请号：US14171734

申请日：2014-02-03

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Chia-Sheng LIN

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L23/525 ,  H01L24/05 ,  H01L24/16 ,  H01L29/0657 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16237 ,  H01L2224/48091 ,  H01L2224/48151 ,  H01L2224/73207 ,  H01L2924/10156 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

Abstract: An embodiment of the disclosure provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed on the first surface and extending into the first recess and/or the second recess; an insulating layer located between the wire layer and the semiconductor substrate; a chip disposed on the first surface; and a conducting structure disposed between the chip and the first surface.

Abstract translation: 本公开的一个实施例提供一种芯片封装，其包括：具有第一表面和第二表面的半导体衬底; 从所述第一表面延伸到所述第二表面的第一凹部; 从所述第一凹部的底部朝向所述第二表面延伸的第二凹部，其中所述第一凹部的侧壁和所述底部以及所述第二凹部的第二侧壁和第二底部一起形成所述半导体衬底的外侧表面; 电线层，其设置在所述第一表面上并延伸到所述第一凹部和/或所述第二凹部中; 位于所述导线层和所述半导体基板之间的绝缘层; 设置在所述第一表面上的芯片; 以及设置在所述芯片和所述第一表面之间的导电结构。

公开(公告)号：US20180358398A1

公开(公告)日：2018-12-13

申请号：US15996841

申请日：2018-06-04

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Po-Han LEE

IPC: H01L27/146 ,  H01L23/00

CPC classification number: H01L27/14636 ,  H01L24/02 ,  H01L24/13 ,  H01L27/14618 ,  H01L27/1462 ,  H01L27/14632 ,  H01L27/14678 ,  H01L27/14685 ,  H01L27/14687 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/13024

Abstract: A chip package includes a chip, an isolation layer, a redistribution layer, a passivation layer, and an encapsulation layer. The chip has a sensor, a conductive pad, a through hole, a top surface, and a bottom surface that is opposite the top surface. The sensor and the conductive pad are located on the top surface, and the conductive pad is in the through hole. The isolation layer is located on the bottom surface of the chip and a sidewall that surrounds the through hole. The redistribution layer is located on the isolation layer, and is in electrical contact with the conductive pad. The passivation layer is located on the isolation layer and the redistribution layer. The encapsulation layer is located on the top surface of the chip and covers the sensor and the conductive pad, and has a flat surface facing away from the chip.

公开(公告)号：US20170148844A1

公开(公告)日：2017-05-25

申请号：US15358852

申请日：2016-11-22

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Hsiao-Lan YEH ,  Chia-Sheng LIN ,  Yi-Ming CHANG ,  Po-Han LEE ,  Hui-Hsien WU ,  Jyun-Liang WU ,  Shu-Ming CHANG ,  Yu-Lung HUANG ,  Chien-Min LIN

IPC: H01L27/146 ,  H01L21/48 ,  H01L21/67 ,  H01L23/18

CPC classification number: H01L27/14698 ,  H01L21/4803 ,  H01L21/67017 ,  H01L21/67132 ,  H01L23/18 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14687

Abstract: A chip package includes a chip, an adhesive layer, and a dam element. The chip has a sensing area, a first surface, and a second surface that is opposite to the first surface. The sensing area is located on the first surface. The adhesive layer covers the first surface of the chip. The dam element is located on the adhesive layer and surrounds the sensing area. The thickness of the dam element is in a range from 20 μm to 750 μm, and the wall surface of the dam element surrounding the sensing area is a rough surface.

公开(公告)号：US20160315061A1

公开(公告)日：2016-10-27

申请号：US15091122

申请日：2016-04-05

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Shu-Ming CHANG ,  Hsing-Lung SHEN

IPC: H01L23/00 ,  H01L21/78 ,  H01L23/31 ,  H01L25/16

CPC classification number: H01L24/17 ,  H01L21/4846 ,  H01L23/147 ,  H01L23/3121 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/16 ,  H01L2224/02372 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/0603 ,  H01L2224/06182 ,  H01L2224/08267 ,  H01L2224/08268 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/16112 ,  H01L2224/16145 ,  H01L2224/16267 ,  H01L2224/16268 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2924/00014 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2224/11 ,  H01L2924/014

Abstract: A chip package includes a first chip and a second chip. The first chip includes a first substrate having a first surface and a second surface opposite to the first surface, a first passive element on the first surface, and a first protection layer covering the first passive element, which the first protection layer has a third surface opposite to the first surface. First and second conductive pad structures are disposed in the first protection layer and electrically connected to the first passive element. The second chip is disposed on the third surface, which the second chip includes an active element and a second passive element electrically connected to the active element. The active element is electrically connected to the first conductive pad structure.

Abstract translation: 芯片封装包括第一芯片和第二芯片。 第一芯片包括具有第一表面和与第一表面相对的第二表面的第一基板，第一表面上的第一无源元件和覆盖第一无源元件的第一保护层，第一保护层具有第三表面 与第一个表面相对。 第一和第二导电焊盘结构设置在第一保护层中并电连接到第一无源元件。 第二芯片设置在第三表面上，第二芯片包括有源元件和与有源元件电连接的第二无源元件。 有源元件电连接到第一导电焊盘结构。

公开(公告)号：US20160315043A1

公开(公告)日：2016-10-27

申请号：US15138119

申请日：2016-04-25

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Shu-Ming CHANG ,  Hsing-Lung SHEN ,  Yu-Hao SU ,  Kuan-Jung WU ,  Yi CHENG

IPC: H01L23/498 ,  H01L21/687 ,  H01L49/02 ,  H01L21/48

CPC classification number: H01L23/49838 ,  C25D17/001 ,  C25D17/005 ,  C25D17/06 ,  H01L21/2885 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/68721 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5227 ,  H01L23/525 ,  H01L23/53214 ,  H01L23/53228 ,  H01L28/10 ,  H01L2224/11

Abstract: A chip package includes a chip, an isolation layer, and a redistribution layer. The chip has a substrate, an electrical pad, and a protection layer. The substrate has a first surface and a second surface. The substrate has a through hole, and protection layer has a concave hole, such that the electrical pad is exposed through the concave hole and the through hole. The isolation layer is located on the second surface, the sidewall of the through hole, and the sidewall of the concave hole. The redistribution layer includes a connection portion and a passive element portion. The connection portion is located on isolation layer and in electrical contact with the electrical pad. The passive element portion is located on isolation layer that is on second surface, and an end of passive element portion is connected to connection portion that is on the second surface.

Abstract translation: 芯片封装包括芯片，隔离层和再分配层。 芯片具有基板，电焊盘和保护层。 基板具有第一表面和第二表面。 基板具有通孔，保护层具有凹孔，使得电焊盘通过凹孔和通孔露出。 隔离层位于第二表面，通孔的侧壁和凹孔的侧壁上。 再分配层包括连接部分和无源元件部分。 连接部分位于隔离层上并与电焊垫电接触。 无源元件部分位于第二表面上的隔离层上，无源元件部分的一端连接到第二表面上的连接部分。

公开(公告)号：US20160171273A1

公开(公告)日：2016-06-16

申请号：US14967153

申请日：2015-12-11

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Shu-Ming CHANG ,  Tsang-Yu LIU ,  Hsing-Lung SHEN

IPC: G06K9/00 ,  H01L21/48 ,  H01L23/498

CPC classification number: G06K9/0002 ,  G06F3/0414 ,  G06K9/00013 ,  H01L2224/141 ,  H01L2224/16225

Abstract: A chip package includes a substrate, a capacitive sensing layer and a computing chip. The substrate has a first surface and a second surface opposite to the first surface, and the capacitive sensing layer is disposed above the second surface and having a third surface opposite to the second surface, which the capacitive sensing layer includes a plurality of capacitive sensing electrodes and a plurality of metal wires. The capacitive sensing electrodes are on the second surface, and the metal wires are on the capacitive sensing electrodes. The computing chip is disposed above the third surface and electrically connected to the capacitive sensing electrodes.

Abstract translation: 芯片封装包括基板，电容感测层和计算芯片。 基板具有与第一表面相对的第一表面和第二表面，并且电容感测层设置在第二表面上方并且具有与第二表面相对的第三表面，电容感测层包括多个电容感测电极 和多根金属线。 电容感测电极位于第二表面上，并且金属线在电容感测电极上。 计算芯片设置在第三表面上方并电连接到电容感测电极。

公开(公告)号：US20160043123A1

公开(公告)日：2016-02-11

申请号：US14819138

申请日：2015-08-05

Applicant: XINTEC INC.

Inventor： Wei-Ming CHIEN ,  Po-Han LEE ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC: H01L27/146

CPC classification number: H01L27/14623 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14685 ,  H01L27/14687 ,  H01L2224/11

Abstract: A semiconductor structure includes a chip, a light transmissive plate, a spacer, and a light-shielding layer. The chip has an image sensor, a first surface and a second surface opposite to the first surface. The image sensor is located on the first surface. The light transmissive plate is disposed on the first surface and covers the image sensor. The spacer is between the light transmissive plate and the first surface, and surrounds the image sensor. The light-shielding layer is located on the first surface between the spacer and the image sensor.

Abstract translation: 半导体结构包括芯片，透光板，间隔物和遮光层。 芯片具有图像传感器，与第一表面相对的第一表面和第二表面。 图像传感器位于第一个表面。 透光板设置在第一表面上并覆盖图像传感器。 间隔物在透光板和第一表面之间，并且围绕图像传感器。 遮光层位于间隔件和图像传感器之间的第一表面上。

公开(公告)号：US20150287619A1

公开(公告)日：2015-10-08

申请号：US14676478

申请日：2015-04-01

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Chia-Sheng LIN ,  Yi-Ming CHANG

IPC: H01L21/67 ,  H01L21/78 ,  B26F3/00 ,  H01L21/683 ,  H01L21/30

CPC classification number: H01L21/67092 ,  B26D1/095 ,  B26D7/1863 ,  H01L21/6838 ,  Y10T83/0267 ,  Y10T225/10 ,  Y10T225/12 ,  Y10T225/364

Abstract: An embodiment of this invention provides a separation apparatus for separating a stacked article, such as a semiconductor chip package with sensing functions, comprising a substrate and a cap layer formed on the substrate. The separation apparatus comprises a vacuum nozzle head including a suction pad having a top surface and a bottom surface, a through hole penetrating the top surface and the bottom surface of the suction pad, and a hollow vacuum pipe connecting the through hole to a vacuum pump; a stage positing under the vacuum nozzle head and substantially aligning with the suction pad; a control means coupling to the vacuum nozzle head to lift upward or lower down the vacuum nozzle head; and a first cutter comprising a first cutting body and a first knife connecting to the first cutting body. The cap layer is pressed against by the bottom surface of the suction pad and sucked by the suction pad of the vacuum nozzle head after the vacuum pump begins to vacuum the air within the hollow vacuum pipe and the through hole. Then, the first cutter cuts into the interface between the substrate and the cap layer, and the cap lay is separated from the substrate by the suction force of the vacuum nozzle head and the lift force generated by the upward movement of the vacuum nozzle head.

Abstract translation: 本发明的一个实施例提供了一种分离装置，用于分离堆叠制品，例如具有感测功能的半导体芯片封装，包括基板和形成在基板上的盖层。 分离装置包括：真空喷嘴头，包括具有顶表面和底表面的吸盘，穿过吸垫的顶表面和底表面的通孔;以及将通孔连接到真空泵的中空真空管 ; 位于真空喷嘴头下方并基本上与吸盘对准的阶段; 连接到真空喷嘴头以将真空喷嘴头向上或向下提升的控制装置; 以及第一切割器，其包括连接到第一切割体的第一切割体和第一切割刀。 在真空泵开始真空吸入中空真空管和通孔中的空气之后，盖层被吸盘的底面压紧并被真空喷嘴头的吸盘吸入。 然后，第一切割器切入基板和盖层之间的界面，并且通过真空喷嘴头的吸力和由真空喷嘴头的向上运动产生的提升力将盖子与基板分离。