专利检索 ap:("Ming-Hung Tseng" OR "Chen-Shien Chen" OR "Chen-Cheng Kuo" OR "Chih-Hua Chen" OR "Ching-Wen Hsiao") AND inv:"Chen-Shien Chen" 第 7 页

61.

发明授权
Fan-out package comprising bulk metal 有权
标题翻译：包括散装金属的扇出包装

公开(公告)号：US08866285B2

公开(公告)日：2014-10-21

申请号：US13604239

申请日：2012-09-05

申请人： Yen-Chang Hu , Chang-Chia Huang , Ching-Wen Hsiao , Chen-Shien Chen

发明人： Yen-Chang Hu , Chang-Chia Huang , Ching-Wen Hsiao , Chen-Shien Chen

IPC分类号： H01L23/04 , H01L23/52

CPC分类号： H01L24/19 , H01L21/568 , H01L23/3128 , H01L23/49861 , H01L23/5389 , H01L24/97 , H01L25/105 , H01L2224/12105 , H01L2224/16227 , H01L2224/19 , H01L2224/32225 , H01L2224/73204 , H01L2224/73267 , H01L2224/97 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2224/81 , H01L2224/83 , H01L2224/83005

摘要： A device includes a polymer, a device die in the polymer, and a plurality of Through Assembly Vias (TAVs) extending from a top surface to a bottom surface of the polymer. A bulk metal feature is located in the polymer and having a top-view size greater than a top-view size of each of the plurality of TAVs. The bulk metal feature is electrically floating. The polymer, the device die, the plurality of TAVs, and the bulk metal feature are portions of a package.

摘要翻译： 该装置包括聚合物，聚合物中的器件管芯，以及从聚合物的顶表面延伸到底表面的多个通孔组件通孔（TAV）。散装金属特征位于聚合物中并且具有大于多个TAV中的每一个的顶视图尺寸的顶视图尺寸。散装金属特征是电浮动的。聚合物，器件芯片，多个TAV和体金属特征是封装的部分。

62.

发明授权
Methods and apparatus for solder on slot connections in package on package structures 有权
标题翻译：封装结构上封装槽上连接焊料的方法和装置

公开(公告)号：US08766441B2

公开(公告)日：2014-07-01

申请号：US13420405

申请日：2012-03-14

申请人： Wei Sen Chang , Ching-Wen Hsiao , Chen-Shien Chen

发明人： Wei Sen Chang , Ching-Wen Hsiao , Chen-Shien Chen

IPC分类号： H01L21/44 , H01L23/498

CPC分类号： H01L24/19 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L2224/02311 , H01L2224/02375 , H01L2224/0239 , H01L2224/024 , H01L2224/03462 , H01L2224/03464 , H01L2224/0401 , H01L2224/04105 , H01L2224/05008 , H01L2224/05012 , H01L2224/05013 , H01L2224/05553 , H01L2224/05569 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/12105 , H01L2224/13022 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/81191 , H01L2224/81192 , H01L2224/81815 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/1035 , H01L2225/1058 , H01L2924/00014 , H01L2924/14 , H01L2924/1433 , H01L2924/1434 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2924/00012 , H01L2224/03 , H01L2924/00 , H01L2224/05552

摘要： Solder on slot connections in package on package structures. An apparatus includes a substrate having a front side surface and a back side surface; a first passivation layer disposed over at least one of the front side and back side surfaces; at least one via opening formed in the first passivation layer; a conductor layer disposed over the first passivation layer, coupled to the at least one via and forming a conductive trace on the surface of the first passivation layer; a second passivation layer formed over the conductor layer; and at least one slot opening formed in the second passivation layer and exposing a portion of the conductive trace for receiving a solder connector. In additional embodiments the substrate may be a semiconductor wafer. Methods for forming the structures are disclosed.

摘要翻译： 焊接在封装结构上的封装上的插槽连接上。一种设备包括：具有前侧表面和后侧表面的基板; 设置在前侧面和后侧表面中的至少一个上的第一钝化层; 形成在所述第一钝化层中的至少一个通孔; 布置在所述第一钝化层上方的导体层，耦合到所述至少一个通孔并在所述第一钝化层的表面上形成导电迹线; 形成在所述导体层上的第二钝化层; 以及形成在所述第二钝化层中并且暴露所述导电迹线的一部分以用于接收焊料连接器的至少一个狭槽开口。在另外的实施例中，衬底可以是半导体晶片。公开了形成结构的方法。

63.

发明申请
Semiconductor Device with Discrete Blocks 有权
标题翻译：具有离散块的半导体器件

公开(公告)号：US20140070422A1

公开(公告)日：2014-03-13

申请号：US13608946

申请日：2012-09-10

申请人： Ching-Wen Hsiao , Chen-Shien Chen , Wei Sen Chang , Yen-Chang Hu

发明人： Ching-Wen Hsiao , Chen-Shien Chen , Wei Sen Chang , Yen-Chang Hu

IPC分类号： H01L23/48 , H01L21/768

CPC分类号： H01L25/0657 , H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/56 , H01L21/6835 , H01L21/6836 , H01L23/3128 , H01L23/3142 , H01L23/481 , H01L23/50 , H01L23/5222 , H01L23/528 , H01L23/538 , H01L23/5389 , H01L23/64 , H01L24/19 , H01L24/24 , H01L2221/68327 , H01L2221/68359 , H01L2224/0231 , H01L2224/02372 , H01L2224/02373 , H01L2224/0401 , H01L2224/04105 , H01L2224/05124 , H01L2224/05147 , H01L2224/05184 , H01L2224/11002 , H01L2224/12105 , H01L2224/13023 , H01L2224/13024 , H01L2224/16225 , H01L2224/16227 , H01L2224/24195 , H01L2224/2518 , H01L2224/73267 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/06572 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/1434 , H01L2924/15311 , H01L2924/181 , H01L2924/19011 , H01L2924/19041 , H01L2924/19043 , H01L2924/19105 , H01L2924/00

摘要： A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having through vias and/or integrated passive devices formed therein are provided. Embodiments such as those disclosed herein may be utilized in PoP applications. In an embodiment, the semiconductor device includes a die and a connection block encased in a molding compound. Interconnection layers may be formed on surfaces of the die, the connection block and the molding compound. One or more dies and/or packages may be attached to the interconnection layers.

摘要翻译： 提供半导体器件和制造方法。特别地，提供了使用具有通孔和/或其中形成的集成无源器件的块的例如分立连接块的半导体器件。诸如本文公开的那些实施例可以用于PoP应用中。在一个实施例中，半导体器件包括模具和封装在模制化合物中的连接块。可以在模具，连接块和模塑料的表面上形成互连层。一个或多个管芯和/或封装可以附接到互连层。

64.

发明授权
Formation of TSV backside interconnects by modifying carrier wafers 有权

公开(公告)号：US08101499B2

公开(公告)日：2012-01-24

申请号：US12751512

申请日：2010-03-31

申请人： Hon-Lin Huang , Ching-Wen Hsiao , Kuo-Ching Hsu , Chen-Shien Chen

发明人： Hon-Lin Huang , Ching-Wen Hsiao , Kuo-Ching Hsu , Chen-Shien Chen

IPC分类号： H01L21/30

摘要： An integrated circuit structure includes a semiconductor wafer, which includes a first notch extending from an edge of the semiconductor wafer into the semiconductor wafer. A carrier wafer is mounted onto the semiconductor wafer. The carrier wafer has a second notch overlapping at least a portion of the first notch. A side of the carrier wafer facing the semiconductor wafer forms a sharp angle with an edge of the carrier wafer. The carrier wafer has a resistivity lower than about 1×108 Ohm-cm.

65.

发明申请
Cooling Channels in 3DIC Stacks 有权
标题翻译： 3DIC堆叠中的冷却通道

公开(公告)号：US20100117201A1

公开(公告)日：2010-05-13

申请号：US12616562

申请日：2009-11-11

申请人： Kai-Ming Ching , Ching-Wen Hsiao , Tsung-Ding Wang , Ming-Hong Tseng , Chen-Shien Chen

发明人： Kai-Ming Ching , Ching-Wen Hsiao , Tsung-Ding Wang , Ming-Hong Tseng , Chen-Shien Chen

IPC分类号： H01L23/48 , H01L23/52

CPC分类号： H01L25/0657 , H01L23/46 , H01L23/473 , H01L23/481 , H01L23/49811 , H01L23/49827 , H01L23/49894 , H01L23/5226 , H01L24/82 , H01L2224/0401 , H01L2224/0557 , H01L2224/06181 , H01L2224/131 , H01L2224/13147 , H01L2225/06513 , H01L2225/06527 , H01L2225/06544 , H01L2225/06589 , H01L2924/00014 , H01L2924/0002 , H01L2924/14 , H01L2924/014 , H01L2224/05552 , H01L2924/00

摘要： An integrated circuit structure includes a die including a semiconductor substrate; dielectric layers over the semiconductor substrate; an interconnect structure including metal lines and vias in the dielectric layers; a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers; and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through.

摘要翻译： 集成电路结构包括：具有半导体衬底的裸片; 半导体衬底上的电介质层; 包括电介质层中的金属线和通孔的互连结构; 从所述半导体衬底的内部延伸到所述电介质层的内部的多个沟道; 以及在所述多个通道的互连结构和密封部分上的电介质膜。多个通道被配置成允许流体流过。

66.

发明授权
Copper bump joint structures with improved crack resistance 有权

公开(公告)号：US09607936B2

公开(公告)日：2017-03-28

申请号：US12619468

申请日：2009-11-16

申请人： Ching-Wen Hsiao , Jiun Yi Wu , Ru-Ying Huang , Chen-Shien Chen

发明人： Ching-Wen Hsiao , Jiun Yi Wu , Ru-Ying Huang , Chen-Shien Chen

IPC分类号： H01L23/488 , H01L23/498 , H01L23/00 , H05K3/34

CPC分类号： H01L23/49816 , H01L23/49827 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/0401 , H01L2224/1146 , H01L2224/1147 , H01L2224/1308 , H01L2224/13083 , H01L2224/13084 , H01L2224/13111 , H01L2224/13116 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/81191 , H01L2224/81193 , H01L2224/81801 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H05K3/3436 , H05K3/3463 , H01L2924/00014 , H01L2224/13099 , H01L2924/00

摘要： An integrated circuit structure includes a first work piece and a second work piece. The first work piece includes a semiconductor substrate, and a copper bump over the semiconductor substrate. The second work piece includes a bond pad. A solder is between and adjoining the first work piece and the second work piece, wherein the solder electrically connects the copper bump to the bond pad. The solder includes palladium.

67.

发明授权
Package-on-Package structures having buffer dams and method for forming the same 有权
标题翻译：具有缓冲堤的封装封装结构及其形成方法

公开(公告)号：US08816507B2

公开(公告)日：2014-08-26

申请号：US13559153

申请日：2012-07-26

申请人： Yen-Chang Hu , Ching-Wen Hsiao , Chen-Shien Chen

发明人： Yen-Chang Hu , Ching-Wen Hsiao , Chen-Shien Chen

IPC分类号： H01L23/48

CPC分类号： H01L21/566 , H01L21/02288 , H01L21/02356 , H01L21/568 , H01L21/6835 , H01L23/3121 , H01L24/19 , H01L25/0657 , H01L25/50 , H01L2221/68372 , H01L2224/04105 , H01L2224/32245 , H01L2224/73267 , H01L2225/06524 , H01L2225/06548 , H01L2225/06589 , H01L2225/06593 , H01L2225/1035 , H01L2924/181 , H01L2924/00

摘要： A device includes a device die and a plurality of metal posts at a surface of the device die and electrically coupled to the device die. The device further includes a plurality of through-assembly vias (TAVs), a dam member between the device die and the plurality of TAVs, and a polymer layer encompassing the device die, the plurality of metal posts, the plurality of TAVs, and the dam member.

摘要翻译： 一种器件包括器件裸片和在器件裸片的表面处的多个金属柱，并且电耦合到器件裸片。该装置还包括多个通过组装通孔（TAV），在器件管芯和多个TAV之间的阻挡构件，以及包围器件管芯，多个金属管柱，多个TAV以及水坝成员

68.

发明申请
Fan-Out Package Comprising Bulk Metal 有权
标题翻译：包括散装金属的扇出包装

公开(公告)号：US20140061937A1

公开(公告)日：2014-03-06

申请号：US13604239

申请日：2012-09-05

申请人： Yen-Chang Hu , Chang-Chia Huang , Ching-Wen Hsiao , Chen-Shien Chen

发明人： Yen-Chang Hu , Chang-Chia Huang , Ching-Wen Hsiao , Chen-Shien Chen

IPC分类号： H01L23/48 , H01L21/60

CPC分类号： H01L24/19 , H01L21/568 , H01L23/3128 , H01L23/49861 , H01L23/5389 , H01L24/97 , H01L25/105 , H01L2224/12105 , H01L2224/16227 , H01L2224/19 , H01L2224/32225 , H01L2224/73204 , H01L2224/73267 , H01L2224/97 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2224/81 , H01L2224/83 , H01L2224/83005

摘要： A device includes a polymer, a device die in the polymer, and a plurality of Through Assembly Vias (TAVs) extending from a top surface to a bottom surface of the polymer. A bulk metal feature is located in the polymer and having a top-view size greater than a top-view size of each of the plurality of TAVs. The bulk metal feature is electrically floating. The polymer, the device die, the plurality of TAVs, and the bulk metal feature are portions of a package.

摘要翻译： 该装置包括聚合物，聚合物中的器件管芯，以及从聚合物的顶表面延伸到底表面的多个通孔组件通孔（TAV）。散装金属特征位于聚合物中并且具有大于多个TAV中的每一个的顶视图尺寸的顶视图尺寸。散装金属特征是电浮动的。聚合物，器件芯片，多个TAV和体金属特征是封装的部分。