公开(公告)号：US10056419B2

公开(公告)日：2018-08-21

申请号：US15895575

申请日：2018-02-13

Applicant: XINTEC INC.

Inventor： Ho-Yin Yiu ,  Ying-Nan Wen ,  Chien-Hung Liu ,  Wei-Chung Yang

IPC: H01L27/146

CPC classification number: H01L27/14634 ,  H01L24/19 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1469 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244

Abstract: A chip package is provided. The chip package includes a sensing device. The chip package also includes a first conductive structure disposed on the sensing device and electrically connected to the sensing device. The chip package further includes a chip and a second conductive structure disposed on the sensing device. The chip includes an integrated circuit device. The second conductive structure is positioned on the chip and is electrically connected to the integrated circuit device and the first conductive structure. In addition, the chip package includes an insulating layer covering the sensing device and the chip. The insulating layer has a hole. The first conductive structure is positioned under the bottom of the hole. The top surface of the insulating layer is coplanar with the top surface of the second conductive structure. A method for forming the chip package is also provided.

公开(公告)号：US09972584B2

公开(公告)日：2018-05-15

申请号：US15140199

申请日：2016-04-27

Applicant: XINTEC INC.

Inventor： Hsing-Lung Shen ,  Jiun-Yen Lai ,  Yu-Ting Huang

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/768 ,  H01L23/31 ,  H01L31/0203 ,  H01L21/78 ,  H01L31/0216 ,  H01L33/62 ,  H01L23/48 ,  H01L21/56

CPC classification number: H01L23/564 ,  H01L21/561 ,  H01L21/76898 ,  H01L21/78 ,  H01L22/32 ,  H01L22/34 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/315 ,  H01L23/3178 ,  H01L23/3185 ,  H01L23/481 ,  H01L31/0203 ,  H01L31/02164 ,  H01L33/62 ,  H01L2224/11

Abstract: A chip package includes a chip, a dam layer, a carrier substrate and a light shielding passivation layer. The chip has a first surface and a second surface opposite to the first surface, and a side surface is disposed between the first surface and the second surface. The dam layer is disposed on the first surface, and the carrier substrate is disposed on the dam layer. The light shielding passivation layer is disposed under the second surface and extended into the carrier substrate to cover the side surface of the chip.

公开(公告)号：US09966358B2

公开(公告)日：2018-05-08

申请号：US15164660

申请日：2016-05-25

Applicant: XINTEC INC.

Inventor： Ho-Yin Yiu ,  Ying-Nan Wen ,  Chien-Hung Liu ,  Wei-Chung Yang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/065 ,  H01L25/00 ,  H01L23/498 ,  H01L23/492 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L25/065 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/4875 ,  H01L23/3128 ,  H01L23/492 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49838 ,  H01L25/0655 ,  H01L25/50 ,  H01L27/14618 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/06586 ,  H01L2924/16235

Abstract: A chip package is provided. The chip package includes a substrate having conductive pads therein and adjacent to a first surface thereof. Chips are attached on a second surface opposite to the first surface of the substrate, and an encapsulation layer covers the chips. First redistribution layers are disposed between the second surface of the substrate and the encapsulation layer, and second redistribution layers are disposed on the encapsulation layer. First conductive structures and second conductive structures are disposed in the encapsulation layer. Each of first and second conductive structures respectively includes at least one bonding ball. The first conductive structures are configured to connect first and second redistribution layers, and the second conductive structures are configured to connect the second redistribution layers and the chip. A method of forming the chip package is also provided.

公开(公告)号：US09881959B2

公开(公告)日：2018-01-30

申请号：US14819348

申请日：2015-08-05

Applicant: XINTEC INC.

Inventor： Po-Shen Lin ,  Chia-Sheng Lin ,  Yi-Ming Chang

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1464 ,  H01L27/14685 ,  H01L27/14687

Abstract: A method of manufacturing chip package includes providing a semiconductor substrate having at least a photo diode and an interconnection layer. The interconnection layer is disposed on an upper surface of the semiconductor substrate and above the photo diode and electrically connected to the photo diode. At least a redistribution circuit is formed on the interconnection layer. The redistribution circuit is electrically connected to the interconnection layer. A packaging layer is formed on the redistribution circuit. Subsequently, a carrier substrate is attached to the packaging layer. A color filter is formed on a lower surface of the semiconductor substrate. A micro-lens module is formed under the color filter. The carrier substrate is removed.

公开(公告)号：US09881889B2

公开(公告)日：2018-01-30

申请号：US14251470

申请日：2014-04-11

Applicant: XINTEC INC.

Inventor： Yu-Lung Huang ,  Shu-Ming Chang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/78 ,  H01L21/66

CPC classification number: H01L24/14 ,  H01L21/78 ,  H01L22/12 ,  H01L22/20 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/11334 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/14131 ,  H01L2224/14145 ,  H01L2224/14177 ,  H01L2224/14179 ,  H01L2224/16058 ,  H01L2224/16227 ,  H01L2224/17051 ,  H01L2224/17517 ,  H01L2224/17519 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/14146 ,  H01L2224/81 ,  H01L2224/81907 ,  H01L2924/00012 ,  H01L2224/11

Abstract: A chip package is provided, in which includes: a packaging substrate, a chip and a plurality solder balls interposed between the packaging substrate and the chip for bonding the packaging substrate and the chip, wherein the solder balls include a first portion of a first size and a second portion of a second size that is different from the first size.

公开(公告)号：US09812413B2

公开(公告)日：2017-11-07

申请号：US14994537

申请日：2016-01-13

Applicant: XINTEC INC.

Inventor： Ho-Yin Yiu ,  Ying-Nan Wen ,  Chien-Hung Liu

IPC: H01L23/00 ,  H01L23/31 ,  H01L29/06

CPC classification number: H01L24/02 ,  H01L23/3114 ,  H01L23/3135 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/81 ,  H01L24/94 ,  H01L29/0657 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00015 ,  H01L2924/0549 ,  H01L2924/10156 ,  H01L2924/15153 ,  H01L2924/3511 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01078 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/0781 ,  H01L2924/0543 ,  H01L2924/01049 ,  H01L2924/0544 ,  H01L2924/0542 ,  H01L2924/0103 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/0231 ,  H01L2224/48

Abstract: A chip module is provided. The chip module includes a chip having an upper surface, a lower surface and a sidewall. The chip includes a signal pad region adjacent to the upper surface. A recess extends from the upper surface toward the lower surface along the sidewall of the chip. A redistribution layer is electrically connected to the signal pad region and extends into the recess. A circuit board is located between the upper surface and the lower surface and extends into the recess. A conducting structure is located in the recess and electrically connects the circuit board to the redistribution layer. A method for forming the chip module is also provided.

公开(公告)号：US09799778B2

公开(公告)日：2017-10-24

申请号：US15157776

申请日：2016-05-18

Applicant: XINTEC INC.

Inventor： Yi-Ying Kuo ,  Ming-Chieh Huang ,  Hsi-Chien Lin

IPC: H01L31/02 ,  H01L31/18 ,  H01L31/0216

CPC classification number: H01L31/02002 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/562 ,  H01L31/0216 ,  H01L31/186 ,  H01L2224/11

Abstract: A chip package includes a chip, an insulating layer, a flowing insulating material layer and conductive layer. The chip has a conductive pad, a side surface, a first surface and a second surface opposite to the first surface, which the side surface is between the first surface and the second surface, and the conductive is below the first surface and protruded from the side surface. The insulating layer covers the second surface and the side surface, and the flowing insulating material layer is disposed below the insulating layer, and the flowing insulating material layer has a trench exposing the conductive pad protruded form the side surface. The conductive layer is disposed below the flowing insulating material layer and extended into the trench to contact the conductive pad.

公开(公告)号：US09780251B2

公开(公告)日：2017-10-03

申请号：US15451202

申请日：2017-03-06

Applicant: XINTEC INC.

Inventor： Wei-Luen Suen ,  Wei-Ming Chien ,  Po-Han Lee ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L31/18 ,  H01L31/02 ,  H01L31/0203 ,  H01L31/0236

CPC classification number: H01L31/02327 ,  H01L21/561 ,  H01L23/3114 ,  H01L31/02002 ,  H01L31/0203 ,  H01L31/02363 ,  H01L31/1804 ,  H01L2224/11

Abstract: A semiconductor structure includes a silicon substrate, a protection layer, an electrical pad, an isolation layer, a redistribution layer, a conductive layer, a passivation layer, and a conductive structure. The silicon substrate has a concave region, a step structure, a tooth structure, a first surface, and a second surface opposite to the first surface. The step structure and the tooth structure surround the concave region. The step structure has a first oblique surface, a third surface, and a second oblique surface facing the concave region and connected in sequence. The protection layer is located on the first surface of the silicon substrate. The electrical pad is located in the protection layer and exposed through the concave region. The isolation layer is located on the first and second oblique surfaces, the second and third surfaces of the step structure, and the tooth structure.

公开(公告)号：US09711469B2

公开(公告)日：2017-07-18

申请号：US14715445

申请日：2015-05-18

Applicant: XINTEC INC.

Inventor： Geng-Peng Pan ,  Yi-Ming Chang ,  Chia-Sheng Lin

IPC: H01L23/00 ,  H01L21/033 ,  H01L21/302 ,  H01L23/48 ,  H01L21/268 ,  H01L21/48 ,  H01L21/768

CPC classification number: H01L24/03 ,  H01L21/0273 ,  H01L21/0334 ,  H01L21/268 ,  H01L21/302 ,  H01L21/48 ,  H01L21/481 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L2224/0231 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/03831 ,  H01L2224/05017 ,  H01L2224/05024 ,  H01L2224/05025 ,  H01L2224/05557 ,  H01L2224/0557 ,  H01L2924/00014

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A first isolation layer is formed on a first surface of a wafer substrate. A conductive pad is formed on the first isolation layer. A hollow region through the first surface and a second surface of the wafer substrate is formed, such that the first isolation layer is exposed through the hollow region. A laser etching treatment is performed on the first isolation layer that is exposed through the hollow region, such that a first opening is formed in the first isolation layer, and a concave portion exposed through the first opening is formed in the conductive pad.

公开(公告)号：US09704772B2

公开(公告)日：2017-07-11

申请号：US15008241

申请日：2016-01-27

Applicant: XINTEC INC.

Inventor： Chien-Hung Liu

IPC: H01L23/29 ,  H01L23/31 ,  H01L21/56 ,  H05K1/18 ,  H05K1/02 ,  H05K1/11 ,  H05K3/32 ,  G06K9/00 ,  G01L19/14 ,  G06F21/32 ,  H01L21/02 ,  G01L19/00 ,  G01L19/06 ,  H01L23/525 ,  H01L21/60

CPC classification number: H01L23/3192 ,  G01L19/0061 ,  G01L19/06 ,  G01L19/14 ,  G06F21/32 ,  G06K9/00 ,  G06K9/00006 ,  H01L21/0212 ,  H01L21/02263 ,  H01L21/56 ,  H01L23/291 ,  H01L23/3114 ,  H01L23/3185 ,  H01L23/525 ,  H01L2021/60022 ,  H01L2224/11 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/181 ,  H05K3/32

Abstract: A chip package includes a chip, a dam layer, a permanent adhesive layer, a support, a buffer layer, a redistribution layer, a passivation layer, and a conducting structure. A conducting pad and a sensing device of the chip are located on a first surface of a substrate of the chip, and the conducting pad protrudes from the side surface of the substrate. The dam layer surrounds the sensing device. The permanent adhesive layer is between the support and the substrate. The support and the permanent adhesive layer have a trench to expose the conducting pad. The buffer layer is located on the support. The redistribution layer is located on the buffer layer and on the support, the permanent adhesive layer, and the conducting pad facing the trench. The passivation layer covers the redistribution layer, the buffer layer, and the conducting pad.