公开(公告)号：US20150340349A1

公开(公告)日：2015-11-26

申请号：US14819189

申请日：2015-08-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Mirng-Ji Lii ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Kai-Chiang Wu

IPC: H01L25/10 ,  H01L25/00 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L24/14 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/11011 ,  H01L2224/14 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0206 ,  H05K1/0306 ,  H05K1/113 ,  H05K2201/068 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A package on packaging structure comprising a first package and a second package provides for improved thermal conduction and mechanical strength by the introduction of a thermally conductive substrate attached to the second package. The first package has a first substrate and a first integrated circuit. The second package has a second substrate containing through vias that has a first coefficient of thermal expansion. The second package also has a second integrated circuit having a second coefficient of thermal expansion located on the second substrate. The second coefficient of thermal expansion deviates from the first coefficient of thermal expansion by less than about 10 or less than about 5 parts-per-million per degree Celsius. A first set of conductive elements couples the first substrate and the second substrate. A second set of conductive elements couples the second substrate and the second integrated circuit.

Abstract translation: 包装结构包括第一包装和第二包装通过引入连接到第二包装件上的导热基材提供改进的热传导和机械强度。 第一封装具有第一衬底和第一集成电路。 第二包装具有包含通孔的第二基板，其具有第一热膨胀系数。 第二封装还具有第二集成电路，其具有位于第二基板上的第二热膨胀系数。 第二热膨胀系数从第一热膨胀系数偏离每摄氏度小于约10或小于约5百万分之一。 第一组导电元件将第一基板和第二基板连接。 第二组导电元件将第二基板和第二集成电路耦合。

公开(公告)号：US09136255B2

公开(公告)日：2015-09-15

申请号：US14196577

申请日：2014-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun-Kyoung Seo ,  Eun-Jin Choi

IPC: H01L25/11 ,  H01L21/56 ,  H01L23/31 ,  H01L23/467 ,  H01L23/498 ,  H01L25/10 ,  H01L25/16 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/117 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/467 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29387 ,  H01L2224/294 ,  H01L2224/29486 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/13099

Abstract: A package stack structure includes a lower semiconductor chip on a lower package substrate having a plurality of lower via plug lands, a lower package having a lower molding compound surrounding a portion of a top surface of the lower package substrate and side surfaces of the lower semiconductor chip, an upper semiconductor chip on an upper package substrate having a plurality of upper via plug lands, an upper package having an upper molding compound covering the upper semiconductor chip, via plugs vertically penetrating the lower molding compound, the via plugs connecting the lower and upper via plug lands, respectively, and a fastening element and an air space between a top surface of the lower molding compound and a bottom surface of the upper package substrate.

Abstract translation: 封装堆叠结构包括在下封装基板上的下半导体芯片，具有多个下通孔插头焊盘，下封装件具有围绕下封装衬底的顶表面的一部分的下模塑料和下半导体的侧表面 芯片，上部封装基板上的上部半导体芯片，具有多个上部通孔插头焊盘，上部封装具有覆盖上部半导体芯片的上部模塑料，通过垂直穿过下部模塑料的插头，连接下部和 分别通过插塞接头和上部封装基板的底面之间的紧固元件和空气间隔。

公开(公告)号：US20150235993A1

公开(公告)日：2015-08-20

申请号：US14181367

申请日：2014-02-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jung Wei Cheng ,  Tsung-Ding Wang ,  Mirng-Ji Lii ,  Chien-Hsun Lee

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L23/367 ,  H01L25/00 ,  H01L21/66

CPC classification number: H01L25/105 ,  H01L22/14 ,  H01L23/13 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/14 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/19 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2224/9222 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2225/1094 ,  H01L2924/12042 ,  H01L2924/15151 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/014

Abstract: An embodiment device includes a first die, a second die electrically connected to the first die, and a heat dissipation surface on a surface of the second die. The device further includes a package substrate electrically connected to the first die. The package substrate includes a through-hole, and the second die is at least partially disposed in the through hole.

Abstract translation: 实施例装置包括第一管芯，与第一管芯电连接的第二管芯，以及在第二管芯的表面上的散热面。 该装置还包括电连接到第一管芯的封装基板。 封装基板包括通孔，并且第二管芯至少部分地设置在通孔中。

公开(公告)号：US20150221621A1

公开(公告)日：2015-08-06

申请号：US14599663

申请日：2015-01-19

Applicant: DENSO CORPORATION

Inventor： Akira MOCHIDA

IPC: H01L25/10 ,  H01L23/495 ,  H05K1/02 ,  H01L23/31

CPC classification number: H01L25/105 ,  H01L23/051 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/4012 ,  H01L23/4334 ,  H01L23/49517 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2225/1029 ,  H01L2225/1094 ,  H01L2924/0002 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor module includes a semiconductor device and a flexible relay member. The semiconductor device includes a resin member, an electronic component sealed with the resin member, and a lead member having an inner lead and an outer lead. The inner lead is located inside the resin member and electrically connected to the electronic component. The outer lead extends from the inner lead and is located outside the resin member. The relay member is electrically connected to the outer lead to electrically connect the electronic component to a connection target to be electrically connected to the semiconductor device.

Abstract translation: 半导体模块包括半导体器件和柔性中继部件。 半导体器件包括树脂部件，用树脂部件密封的电子部件，以及具有内部引线和外部引线的引线部件。 内引线位于树脂构件的内部并与电子部件电连接。 外引线从内引线延伸并位于树脂构件外部。 继电器构件电连接到外引线，以将电子部件电连接到电连接到半导体器件的连接对象。

公开(公告)号：US20150206869A1

公开(公告)日：2015-07-23

申请号：US14516764

申请日：2014-10-17

Applicant: Jongkook KIM ,  Jangwoo LEE ,  Kyoungsei CHOI ,  Sayoon KANG ,  Donghan KIM ,  Hwanggil SHIM

Inventor： Jongkook KIM ,  Jangwoo LEE ,  Kyoungsei CHOI ,  Sayoon KANG ,  Donghan KIM ,  Hwanggil SHIM

IPC: H01L25/00

CPC classification number: H01L23/36 ,  H01L23/42 ,  H01L23/49816 ,  H01L23/552 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Package-on-package (POP) devices and methods of manufacturing the POP devices are provided. In the POP devices, a thermal interface material layer disposed between lower and upper semiconductor packages may contact about 70% or greater of an area of a top surface of a lower semiconductor chip. According to methods, the upper semiconductor package may be mounted on the lower semiconductor chip using a weight.

Abstract translation: 提供封装（POP）设备和制造POP设备的方法。 在POP装置中，设置在下半导体封装和上半导体封装之间的热界面材料层可以接触下半导体芯片的顶表面的大约70％或更大的面积。 根据方法，上半导体封装可以使用重量安装在下半导体芯片上。

公开(公告)号：US20150160701A1

公开(公告)日：2015-06-11

申请号：US14097491

申请日：2013-12-05

Applicant: Apple Inc.

Inventor： John Bruno ,  Jun Zhai ,  Timothy J. Millet

IPC: G06F1/18

CPC classification number: H01L25/18 ,  H01L23/13 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/13124 ,  H01L2224/134 ,  H01L2224/13411 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/0204 ,  H05K1/141 ,  H05K1/144 ,  H05K1/181 ,  H05K2201/09036 ,  H05K2201/10416 ,  H05K2201/10734 ,  H01L2924/014

Abstract: A semiconductor package includes a processor die (e.g., an SoC) and one or more memory die (e.g., DRAM) coupled to a ball grid array (BGA) substrate. The processor die and the memory die are coupled to opposite sides of the BGA substrate using terminals (e.g., solder balls). The package may be coupled to a printed circuit board (PCB) using one or more terminals positioned around the perimeter of the processor die. The PCB may include a recess with at least part of the processor die being positioned in the recess. Positioning at least part of the processor die in the recess reduces the overall height of the semiconductor package assembly. A voltage regulator may also be coupled to the BGA substrate on the same side as the processor die with at least part of the voltage regulator being positioned in the recess a few millimeters from the processor die.

Abstract translation: 半导体封装包括耦合到球栅阵列（BGA）衬底的处理器管芯（例如，SoC）和一个或多个存储器管芯（例如，DRAM）。 使用端子（例如，焊球）将处理器管芯和存储器管芯耦合到BGA衬底的相对侧。 可以使用位于处理器管芯的周边周围的一个或多个端子将封装耦合到印刷电路板（PCB）。 PCB可以包括凹部，其中处理器管芯的至少一部分位于凹部中。 将处理器管芯的至少一部分定位在凹部中减小了半导体封装组件的整体高度。 电压调节器还可以与处理器管芯相同侧的BGA衬底耦合，其中至少一部分电压调节器位于距离处理器管芯几毫米的凹槽中。

公开(公告)号：US20150130046A1

公开(公告)日：2015-05-14

申请号：US14514360

申请日：2014-10-14

Applicant: BRIDGE SEMICONDUCTOR CORPORATION

Inventor： Charles W. C. Lin ,  Chia-Chung Wang

IPC: H01L23/36 ,  H01L23/498

CPC classification number: H01L25/105 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81203 ,  H01L2224/81207 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2225/1094 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/1531 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/15793 ,  H01L2924/16153 ,  H01L2924/16172 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/16724 ,  H01L2924/16747 ,  H01L2924/1676 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: The present invention relates to a method of making a semiconductor package with package-on-package stacking capability. In accordance with a preferred embodiment, the method is characterized by the step of attaching a chip-on-interposer subassembly on a metallic carrier with the chip inserted into a cavity of the metallic carrier, and the step of selectively removing portions of the metallic carrier to define a heat spreader for the chip. The heat spreader can provide thermal dissipation, electromagnetic shielding and moisture barrier, whereas the interposer provides a CTE-matched interface and fan-out routing for the chip.

Abstract translation: 本发明涉及制造具有封装封装堆叠能力的半导体封装的方法。 根据优选实施例，该方法的特征在于将芯片插入器子组件附接到金属载体上，其中芯片插入金属载体的空腔中，并且选择性地去除金属载体的部分的步骤 为芯片定义散热器。 散热器可以提供散热，电磁屏蔽和防潮，而插入器为芯片提供了CTE匹配的接口和扇出路由。

公开(公告)号：US09029989B2

公开(公告)日：2015-05-12

申请号：US13969053

申请日：2013-08-16

Applicant: Soojeoung Park

Inventor： Soojeoung Park

IPC: H01L21/48 ,  H01L23/373 ,  H01L23/552 ,  H01L23/36 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/373 ,  H01L23/36 ,  H01L23/552 ,  H01L25/0652 ,  H01L25/105 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A semiconductor package includes a substrate, a ground circuit supported by the substrate, at least one semiconductor chip disposed on the substrate and a carbon-containing heat-dissipating part disposed on the substrate and electrically connected to the ground circuit. The heat-dissipating part may include carbon fibers and/or carbon cloth.

Abstract translation: 半导体封装包括衬底，由衬底支撑的接地电路，设置在衬底上的至少一个半导体芯片和设置在衬底上并与接地电路电连接的含碳散热部分。 散热部件可以包括碳纤维和/或碳布。

公开(公告)号：US20150115424A1

公开(公告)日：2015-04-30

申请号：US14524906

申请日：2014-10-27

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Jean-Michel Riviere ,  Nadine Martin

IPC: H01L23/495 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/5389 ,  H01L25/105 ,  H01L2023/4056 ,  H01L2023/4062 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An electronic system includes a first electronic device (with a first integrated-circuit chip) and a second electronic device (with a second integrated-circuit chip). The second electronic device is stacked above the first electronic device on a same side as the first integrated-circuit chip. Electrical connection elements located around the first integrated-circuit chip electrically connected to the second electronic device to the first electronic device. A metal plate configured for heat capture and transfer extends between the first and second electronic devices. The metal plate includes through-passages aligned to permit the electrical connection elements to pass at a distance.

Abstract translation: 电子系统包括第一电子设备（具有第一集成电路芯片）和第二电子设备（具有第二集成电路芯片）。 第二电子装置在与第一集成电路芯片相同的一侧堆叠在第一电子装置的上方。 电连接元件围绕第一集成电路芯片电连接到第二电子设备到第一电子设备。 配置用于捕获和传送的金属板在第一和第二电子设备之间延伸。 金属板包括对准以允许电连接元件一段距离通过的通孔。

公开(公告)号：US09013040B1

公开(公告)日：2015-04-21

申请号：US14045226

申请日：2013-10-03

Applicant: Jon Schmidt

Inventor： Jon Schmidt

IPC: H01L21/60 ,  H01L23/498 ,  H01L21/768 ,  H01L25/18 ,  H01L23/34 ,  H01L23/00

CPC classification number: H01L24/17 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/481 ,  H01L23/49555 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16227 ,  H01L2224/24101 ,  H01L2224/24227 ,  H01L2224/245 ,  H01L2224/291 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48159 ,  H01L2224/48227 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/821 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15153 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/16152 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A memory device with die stacking is provided. A plurality of substrates layers are stacked together into a stack. Each substrate layer may include a substrate having a plurality of cavities to receive integrated circuit components within the thickness of the substrate. A plurality of conductive spheres are arranged between at least two adjacent substrate layers and are electrically coupled to the integrated circuit components in at least one of the two adjacent substrates. The two adjacent substrate layers of the stack include: (a) a first substrate having a first plurality of cavities to receive integrated circuit components, and (b) a second substrate having a second plurality of cavities to receive integrated circuit components, wherein the first plurality of cavities is offset from a second plurality of cavities.

Abstract translation: 提供了具有管芯堆叠的存储器件。 多个基板层堆叠成堆叠。 每个衬底层可以包括具有多个空腔的衬底，以在衬底的厚度内接收集成电路部件。 多个导电球布置在至少两个相邻的基底层之间，并且在两个相邻基底中的至少一个中电连接到集成电路部件。 堆叠的两个相邻的衬底层包括：（a）具有第一多个空腔以接收集成电路部件的第一衬底，以及（b）具有第二多个腔以接收集成电路部件的第二衬底，其中第一衬底 多个空腔与第二多个空腔偏移。