公开(公告)号：US20180090444A1

公开(公告)日：2018-03-29

申请号：US15711819

申请日：2017-09-21

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Sang Jin LEE ,  Dong Hun LEE

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/5389 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L29/06 ,  H01L2224/0231 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05124 ,  H01L2224/05569 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/21 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/73204 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/10156 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/35121 ,  H01L2924/00014

Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant filling at least portions of spaces between walls of the through-hole and side surfaces of the semiconductor chip; and a second interconnection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip through vias, wherein the side surface of the semiconductor chip has a step portion.

公开(公告)号：US20180040526A1

公开(公告)日：2018-02-08

申请号：US15666858

申请日：2017-08-02

Applicant: ABB Schweiz AG ,  Audi AG

Inventor： Jürgen Schuderer ,  Umamaheswara Vemulapati ,  Marco Bellini ,  Jan Vobecky

IPC: H01L23/14 ,  H01L25/18 ,  H01L23/538 ,  H01L29/06 ,  H01L23/535

CPC classification number: H01L23/147 ,  H01L23/36 ,  H01L23/3736 ,  H01L23/535 ,  H01L23/5386 ,  H01L23/62 ,  H01L25/072 ,  H01L25/18 ,  H01L29/0634 ,  H01L29/0646 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2924/00014 ,  H01L2924/10252 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/1301 ,  H01L2924/1304 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A power semiconductor module including at least one power semiconductor chip providing a power electronics switch; and a semiconductor wafer, to which the at least one power semiconductor chip is bonded; wherein the semiconductor wafer is doped, such that it includes a field blocking region and an electrically conducting region on the field blocking region, to which electrically conducting region the at least one power semiconductor chip is bonded.

公开(公告)号：US20180025994A1

公开(公告)日：2018-01-25

申请号：US15529072

申请日：2015-11-24

Applicant: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY

Inventor： Shiro HARA ,  Sommawan KHUMPUANG ,  Fumito IMURA ,  Michihiro INOUE ,  Arami SARUWATARI

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L23/538 ,  H01L23/367

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4871 ,  H01L21/563 ,  H01L23/12 ,  H01L23/295 ,  H01L23/296 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/214 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/83805 ,  H01L2224/83851 ,  H01L2224/92244 ,  H01L2924/10155 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10254 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/1301 ,  H01L2924/1304 ,  H01L2924/14 ,  H01L2924/1432 ,  H01L2924/1461 ,  H01L2924/35121

Abstract: An object of the present invention is to provide a surface-mount type package for semiconductor chips which is resistant to failures caused by thermal stress. As a means for achieving the object, a method for manufacturing a surface-mount type package whose face parallel with the semiconductor chip surface has a circular cross-section, is provided, wherein such method is characterized in that it comprises at least the following steps in this order.A first step in which a semiconductor chip is bonded onto a circular support substrate.A second step in which the semiconductor chip is sealed with resin.A third step in which the resin covering the pads of the semiconductor chip is removed.A fourth step in which a rewiring layer is formed.A fifth step in which bumps are formed.

公开(公告)号：US09875970B2

公开(公告)日：2018-01-23

申请号：US15413713

申请日：2017-01-24

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Moon Hee Yi ,  Joo Hwan Jung ,  Yul Kyo Chung

IPC: H01L23/34 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L23/367

CPC classification number: H01L23/5389 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/14 ,  H01L24/20 ,  H01L2224/02311 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/14177 ,  H01L2224/19 ,  H01L2224/215 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1579 ,  H01L2924/186 ,  H01L2924/19105 ,  H01L2924/3025

Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; a pattern layer disposed on the encapsulant and covering at least portions of the encapsulant adjacent to the inactive surface of the semiconductor chip; vias penetrating through the encapsulant and connecting the pattern layer and the inactive surface of the semiconductor chip to each other; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip.

公开(公告)号：US09831156B2

公开(公告)日：2017-11-28

申请号：US15076141

申请日：2016-03-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jing-Cheng Lin

IPC: H01L21/76 ,  H01L23/48 ,  H01L21/768 ,  H01L27/06 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/762

CPC classification number: H01L23/481 ,  H01L21/76224 ,  H01L21/76898 ,  H01L24/80 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05563 ,  H01L2224/05564 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/08147 ,  H01L2224/13 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/80013 ,  H01L2224/80075 ,  H01L2224/80091 ,  H01L2224/80095 ,  H01L2224/80896 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10333 ,  H01L2924/10335 ,  H01L2924/10338 ,  H01L2924/10342 ,  H01L2224/80 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

Abstract: Methods for forming a semiconductor device structure are provided. The method includes providing a first semiconductor wafer and a second semiconductor wafer. A first transistor is formed in a front-side of the first semiconductor wafer, and no devices are formed in the second semiconductor wafer. The method further includes bonding the front-side of the first semiconductor wafer to a backside of the second semiconductor wafer and thinning a front-side of the second semiconductor wafer. After thinning the second semiconductor wafer, a second transistor is formed in the front-side of the second semiconductor wafer. At least one first through substrate via (TSV) is formed in the second semiconductor wafer, and the first TSV directly contacts a conductive feature of the first semiconductor wafer.

公开(公告)号：US20170256487A1

公开(公告)日：2017-09-07

申请号：US15601734

申请日：2017-05-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Hsien-Wei Chen ,  An-Jhih Su ,  Chi-Hsi Wu ,  Der-Chyang Yeh ,  Shih-Peng Tai

IPC: H01L23/528 ,  H01L21/02 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/535 ,  H01L23/538

CPC classification number: H01L23/528 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/311 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/525 ,  H01L23/5286 ,  H01L23/535 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10331 ,  H01L2924/10332 ,  H01L2924/10333 ,  H01L2924/10335 ,  H01L2924/10339 ,  H01L2924/10342 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436

Abstract: Semiconductor device, multi-die packages, and methods of manufacture thereof are described. In an embodiment, a semiconductor device may include: first conductive pillars and second conductive pillars respectively aligned to a first row of first pins and a second row of second pins of a first die, the first pins and the second pins differing in function; a first insulating layer covering surfaces of the first conductive pillars and the second conductive pillars facing away from the first die; first pads disposed on a surface of the first insulating layer facing away from the first die, the first pads substantially aligned to the first conductive pillars; and first traces coupled to the first pads, the first traces extending over a portion of the first insulating layer covering the second conductive pillars.

公开(公告)号：US20170229436A1

公开(公告)日：2017-08-10

申请号：US15496842

申请日：2017-04-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Der-Chyang Yeh ,  An-Jhih Su

IPC: H01L25/16 ,  H01L23/538 ,  H01L23/00 ,  H01L23/58 ,  H01L21/56 ,  H01L25/00 ,  H01L23/50

CPC classification number: H01L25/16 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L22/32 ,  H01L23/50 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/58 ,  H01L24/03 ,  H01L24/09 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10333 ,  H01L2924/10335 ,  H01L2924/10342 ,  H01L2924/14 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/18162 ,  H01L2224/03

Abstract: Various packages and methods of forming packages are discussed. According to an embodiment, a package includes a processor die at least laterally encapsulated by an encapsulant, a memory die at least laterally encapsulated by the encapsulant, and a redistribution structure on the encapsulant. The processor die is communicatively coupled to the memory die through the redistribution structure. According to further embodiments, the memory die can include memory that is a cache of the processor die, and the memory die can comprise dynamic random access memory (DRAM).

公开(公告)号：US09691707B2

公开(公告)日：2017-06-27

申请号：US15130452

申请日：2016-04-15

Applicant: STATS ChipPAC, Ltd.

Inventor： HeeJo Chi ,  HanGil Shin ,  NamJu Cho

IPC: H01L23/48 ,  H01L23/02 ,  H01L21/00 ,  H01L23/538 ,  H01L23/528 ,  H01L21/768 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L24/19 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/528 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/73 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/6834 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68386 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/08235 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/19 ,  H01L2224/24227 ,  H01L2224/25171 ,  H01L2224/82039 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10322 ,  H01L2924/10324 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10335 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/153 ,  H01L2924/181 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/82 ,  H01L2224/08

Abstract: A semiconductor device has a plurality of semiconductor die. A substrate is provided with bumps disposed over the substrate. A first prefabricated insulating film is disposed between the semiconductor die and substrate. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The bumps include a copper core encapsulated within copper plating. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The substrate includes a conductive layer formed in the substrate and coupled to the bumps. The semiconductor die is disposed between the bumps of the substrate. The bumps and the semiconductor die are embedded within the first prefabricated insulating film. A portion of the first prefabricated insulating film is removed to expose the bumps. The bumps electrically connect the substrate to the interconnect structure.

公开(公告)号：US20170125376A1

公开(公告)日：2017-05-04

申请号：US15379590

申请日：2016-12-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sung-Feng Yeh ,  Chen-Hua Yu ,  Ming-Fa Chen

IPC: H01L25/065 ,  H01L23/31 ,  H01L21/56 ,  H01L25/00 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/315 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/80 ,  H01L24/83 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/08145 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73209 ,  H01L2224/73267 ,  H01L2224/80006 ,  H01L2224/8203 ,  H01L2224/83896 ,  H01L2224/92124 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10331 ,  H01L2924/10332 ,  H01L2924/10333 ,  H01L2924/10335 ,  H01L2924/10338 ,  H01L2924/10339 ,  H01L2924/10342 ,  H01L2924/14 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1816 ,  H01L2924/18162 ,  H01L2224/80 ,  H01L2224/83005

Abstract: An embodiment method for forming a semiconductor package includes attaching a first die to a first carrier, depositing a first isolation material around the first die, and after depositing the first isolation material, bonding a second die to the first die. Bonding the second die to the first die includes forming a dielectric-to-dielectric bond. The method further includes removing the first carrier and forming fan-out redistribution layers (RDLs) on an opposing side of the first die as the second die. The fan-out RDLs are electrically connected to the first die and the second die.

公开(公告)号：US09627349B2

公开(公告)日：2017-04-18

申请号：US14909157

申请日：2013-09-13

Applicant: EV GROUP E. THALLNER GMBH

Inventor： Markus Wimplinger

IPC: H01L23/00 ,  B81C3/00

CPC classification number: H01L24/83 ,  B81C3/001 ,  B81C2203/036 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/29082 ,  H01L2224/291 ,  H01L2224/29105 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29117 ,  H01L2224/29118 ,  H01L2224/29123 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29157 ,  H01L2224/2916 ,  H01L2224/29166 ,  H01L2224/29169 ,  H01L2224/29171 ,  H01L2224/29184 ,  H01L2224/32145 ,  H01L2224/32507 ,  H01L2224/8302 ,  H01L2224/83022 ,  H01L2224/8381 ,  H01L2224/83894 ,  H01L2924/01003 ,  H01L2924/01005 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01034 ,  H01L2924/01037 ,  H01L2924/01038 ,  H01L2924/0105 ,  H01L2924/01052 ,  H01L2924/01055 ,  H01L2924/01056 ,  H01L2924/01322 ,  H01L2924/10251 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/1026 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10323 ,  H01L2924/10328 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10331 ,  H01L2924/10332 ,  H01L2924/10333 ,  H01L2924/10334 ,  H01L2924/10335 ,  H01L2924/10336 ,  H01L2924/10346 ,  H01L2924/1037 ,  H01L2924/10371 ,  H01L2924/10372 ,  H01L2924/10373 ,  H01L2924/10375 ,  H01L2924/10376 ,  H01L2924/10377 ,  H01L2924/10821 ,  H01L2924/10823 ,  H01L2924/10831 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2924/01013 ,  H01L2924/01031 ,  H01L2924/0103

Abstract: A method for applying a bonding layer that is comprised of a basic layer and a protective layer on a substrate with the following method steps: application of an oxidizable basic material as a basic layer on a bonding side of the substrate, at least partial covering of the basic layer with a protective material that is at least partially dissolvable in the basic material as a protective layer. In addition, the invention relates to a corresponding substrate.