公开(公告)号：US20090283870A1

公开(公告)日：2009-11-19

申请号：US12121682

申请日：2008-05-15

申请人： Reza A. Pagaila ,  Linda Pei Ee Chua ,  Byung Tai Do

发明人： Reza A. Pagaila ,  Linda Pei Ee Chua ,  Byung Tai Do

IPC分类号： H01L23/538 ,  H01L21/304

CPC分类号： H01L24/24 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/19 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/24137 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/82001 ,  H01L2225/0651 ,  H01L2225/06551 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device is made by disposing a plurality of semiconductor die on a carrier and creating a gap between each of the semiconductor die. A first insulating material is deposited in the gap. A portion of the first insulating material is removed. A conductive layer is formed over the semiconductor die. A conductive lining is conformally formed on the remaining portion of the first insulating material to form conductive via within the gap. The conductive vias can be tapered or vertical. The conductive via is electrically connected to a contact pad on the semiconductor die. A second insulating material is deposited in the gap over the conductive lining. A portion of the conductive via may extend outside the first and second insulating materials. The semiconductor die are singulated through the gap. The semiconductor die can be stacked and interconnected through the conductive vias.

摘要翻译： 通过将多个半导体管芯设置在载体上并在每个半导体管芯之间产生间隙来制造半导体器件。 第一绝缘材料沉积在间隙中。 去除第一绝缘材料的一部分。 在半导体管芯上形成导电层。 在第一绝缘材料的剩余部分上保形地形成导电衬里，以在间隙内形成导电通孔。 导电通孔可以是锥形或垂直的。 导电通孔电连接到半导体管芯上的接触焊盘。 第二绝缘材料沉积在导电衬里上的间隙中。 导电通孔的一部分可以延伸到第一和第二绝缘材料的外部。 半导体管芯通过间隙被切割。 半导体管芯可以通过导电通孔堆叠和互连。

公开(公告)号：US07618846B1

公开(公告)日：2009-11-17

申请号：US12140092

申请日：2008-06-16

申请人： Reza A. Pagaila ,  Byung Tai Do ,  Rui Huang

发明人： Reza A. Pagaila ,  Byung Tai Do ,  Rui Huang

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L25/105 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/29 ,  H01L23/3114 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L24/82 ,  H01L24/96 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/12105 ,  H01L2224/48091 ,  H01L2224/48471 ,  H01L2224/73265 ,  H01L2224/85385 ,  H01L2225/06527 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device has a semiconductor die with a peripheral region around the die. A first insulating material is deposited in the peripheral region. A conductive via is formed through the first insulating material. A conductive layer is formed over the semiconductor die. The conductive layer is electrically connected between the conductive via and a contact pad of the semiconductor die. A second insulating layer is deposited over the first insulating layer, conductive layer, and semiconductor die. A profile is formed in the first and second insulating layers in the peripheral region. The profile is tapered, V-shaped, truncated V-shape, flat, or vertical. A shielding layer is formed over the first and second insulating layers to isolate the semiconductor die from inter-device interference. The shielding layer conforms to the profile in the peripheral region and electrically connects the shielding layer to the conductive via.

摘要翻译： 半导体器件具有半导体管芯，该半导体管芯具有围绕管芯的周边区域。 第一绝缘材料沉积在周边区域中。 通过第一绝缘材料形成导电通孔。 在半导体管芯上形成导电层。 导电层电连接在导电通孔和半导体管芯的接触焊盘之间。 在第一绝缘层，导电层和半导体管芯上沉积第二绝缘层。 在周边区域的第一绝缘层和第二绝缘层中形成轮廓。 型材呈锥形，V形，截头V形，扁平或垂直。 在第一绝缘层和第二绝缘层之上形成屏蔽层以将半导体管芯与器件间干扰隔离。 屏蔽层符合外围区域中的轮廓并将屏蔽层电连接到导电通孔。

公开(公告)号：US07612444B2

公开(公告)日：2009-11-03

申请号：US11620553

申请日：2007-01-05

申请人： Seng Guan Chow ,  Oh Sug Kim ,  Byung Tai Do

发明人： Seng Guan Chow ,  Oh Sug Kim ,  Byung Tai Do

IPC分类号： H01L23/488 ,  H01L23/48 ,  H01L21/56

CPC分类号： H01L25/0657 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package can comprise a die stack attached to a substrate, with bond wires electrically connecting the two. Often multiple die stacks are adhered to a single substrate so that several semiconductor packages can be manufactured at once. A molding compound flow controller is optimally associated with the substrate or semiconductor package at one or more various locations. Flow controllers can control or direct the flow of the molding compound during the encapsulation process. Flow controllers can be sized, shaped, and positioned in order to smooth out the flow of the molding compound, such that the speed of the flow is substantially equivalent over areas of the substrate containing dies and over areas of the substrate without dies. In this manner, defects such as voids in the encapsulation, wire sweeping, and wire shorts can be substantially avoided during encapsulation.

摘要翻译： 半导体封装可以包括附接到衬底的管芯堆叠，其中接合线电连接两者。 通常，多个管芯堆叠被粘附到单个衬底上，使得可以一次制造几个半导体封装。 模制复合流量控制器在一个或多个不同位置处与衬底或半导体封装最佳地相关联。 流动控制器可以在封装过程中控制或引导模塑料的流动。 流量控制器的尺寸，形状和位置可以平滑模制化合物的流动，从而在含有模具的基材的区域和没有模具的基材的超过区域上流动的速度基本相当。 以这种方式，在封装期间可以基本上避免诸如封装，电线清扫和电线短路之类的缺陷的缺陷。

公开(公告)号：US20090212401A1

公开(公告)日：2009-08-27

申请号：US12037774

申请日：2008-02-26

申请人： Byung Tai Do ,  Rui Huang ,  Seng Guan Chow ,  Heap Hoe Kuan

发明人： Byung Tai Do ,  Rui Huang ,  Seng Guan Chow ,  Heap Hoe Kuan

IPC分类号： H01L23/552 ,  H01L21/56

CPC分类号： H01L23/3128 ,  H01L21/56 ,  H01L23/552 ,  H01L24/48 ,  H01L24/73 ,  H01L24/91 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： The present invention provides a package system including: providing a semiconductor die with a contact pad and a ground pad, mounting the semiconductor die on a package substrate using and adhesive layer, forming a vertical conductive structure on top of the ground pad in the semiconductor die, encapsulating at least portions of the semiconductor die, the vertical conductive structure, and the package substrate using an encapsulant, covering at least portions of the encapsulant and the vertical conductive structure with a shielding layer to place the vertical conductive structure in electrical contact with the shielding layer, and connecting the shielding layer to the package substrate.

摘要翻译： 本发明提供了一种封装系统，包括：提供具有接触焊盘和接地焊盘的半导体管芯，使用粘合剂层将半导体管芯安装在封装衬底上，在半导体管芯中的接地焊盘顶部形成垂直导电结构 ，使用密封剂封装半导体管芯，垂直导电结构和封装衬底的至少一部分，用屏蔽层覆盖至少一部分密封剂和垂直导电结构，以使垂直导电结构与 屏蔽层，并且将屏蔽层连接到封装基板。

公开(公告)号：US07569421B2

公开(公告)日：2009-08-04

申请号：US11744657

申请日：2007-05-04

申请人： Byung Tai Do ,  Heap Hoe Kuan

发明人： Byung Tai Do ,  Heap Hoe Kuan

IPC分类号： H01L21/00

CPC分类号： H01L23/49805 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3185 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2224/02371 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/45139 ,  H01L2224/48145 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/15173 ,  H01L2924/15313 ,  H01L2924/15787 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor device is manufactured by, first, providing a wafer designated with a saw street guide. The wafer is taped with a dicing tape. The wafer is singulated along the saw street guide into a plurality of dies having a plurality of gaps between each of the plurality of dies. The dicing tape is stretched to expand the plurality of gaps to a predetermined distance. An organic material is deposited into each of the plurality of gaps. A top surface of the organic material is substantially coplanar with a top surface of a first die of the plurality of dies. A plurality of via holes is formed in the organic material. Each of the plurality of via holes is patterned to each of a plurality of bond pad locations on the plurality of dies. A conductive material is deposited in each of the plurality of via holes.

摘要翻译： 半导体器件通过首先提供指定有锯条导轨的晶片来制造。 晶片用切割胶带胶带。 将晶片沿着锯条导轨分割为具有在多个模具中的每一个之间具有多个间隙的多个模具。 切割带被拉伸以将多个间隙扩展到预定距离。 有机材料沉积在多个间隙中的每一个中。 有机材料的顶表面与多个管芯的第一管芯的顶表面基本共面。 在有机材料中形成多个通孔。 多个通孔中的每一个被图案化成多个管芯上的多个接合焊盘位置中的每一个。 导电材料沉积在多个通孔中的每一个中。

公开(公告)号：US07566650B2

公开(公告)日：2009-07-28

申请号：US11162822

申请日：2005-09-23

申请人： Yaojian Lin ,  Byung Tai Do ,  Romeo Emmanuel P. Alvarez

发明人： Yaojian Lin ,  Byung Tai Do ,  Romeo Emmanuel P. Alvarez

IPC分类号： H01L21/44 ,  H01L21/4763

CPC分类号： H01L24/06 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14104 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00012

摘要： An integrated circuit solder bumping system provides a substrate and forms a redistribution layer on the substrate. An insulation layer is formed on the redistribution layer. The insulation layer has a plurality of openings therethrough. A first UBM layer of titanium is deposited on the insulation layer and in the openings therethrough. A second UBM layer of chromium/copper alloy is deposited on the first UBM layer. A third UBM layer of copper is deposited on the second UBM layer. UBM pads of at least two different sizes are formed from the UBM layers. Solder paste is printed over at least some of the UBM pads. The solder paste is reflowed to form at least smaller solder bumps on at least some of the UBM pads. Bigger solder bumps are formed on at least some of the UBM pads.

摘要翻译： 集成电路焊料凸块系统提供衬底并在衬底上形成再分布层。 在再分布层上形成绝缘层。 绝缘层具有穿过其中的多个开口。 第一UBM层钛沉积在绝缘层上和通过其中的开口中。 第二UBM层的铬/铜合金沉积在第一UBM层上。 铜的第三UBM层沉积在第二UBM层上。 具有至少两种不同尺寸的UBM焊盘由UBM层形成。 至少一些UBM垫上印有焊膏。 焊膏被回流以在至少一些UBM焊盘上形成至少较小的焊料凸块。 在至少一些UBM垫上形成更大的焊料凸块。

公开(公告)号：US20090166824A1

公开(公告)日：2009-07-02

申请号：US11964567

申请日：2007-12-26

申请人： Byung Tai Do ,  Linda Pei Ee Chua ,  Heap Hoe Kuan

发明人： Byung Tai Do ,  Linda Pei Ee Chua ,  Heap Hoe Kuan

IPC分类号： H01L23/495 ,  H01L21/60

CPC分类号： H01L23/49548 ,  H01L21/4832 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/49582 ,  H01L24/16 ,  H01L24/28 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/13099 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/73265 ,  H01L2224/85411 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

摘要： A leadless package system includes: providing a chip carrier having indentations defining a pattern for a protrusion for external contact terminals; placing an external coating layer in the indentations in the chip carrier; layering a conductive layer on top of the external coating layer; depositing an internal coating layer on the conductive layer; patterning the internal coating layer and the conductive layer to define external contact terminals with a T-shape profile; connecting an integrated circuit die to the external contact terminals; encapsulating the integrated circuit die and external contact terminals; and separating the chip carrier from the external coating layer.

摘要翻译： 无引线封装系统包括：提供具有限定用于外部接触端子的突起的图案的凹口的芯片载体; 将外部涂层置于芯片载体的凹陷中; 在外部涂层的顶部上分层导电层; 在导电层上沉积内部涂层; 图案化内部涂层和导电层以限定具有T形轮廓的外部接触端子; 将集成电路管芯连接到外部接触端子; 封装集成电路管芯和外部接触端子; 并且将芯片载体与外部涂层分离。

公开(公告)号：US20080274603A1

公开(公告)日：2008-11-06

申请号：US11861233

申请日：2007-09-25

申请人： Byung Tai DO ,  Heap Hoe KUAN ,  Linda Pei Ee CHUA

发明人： Byung Tai DO ,  Heap Hoe KUAN ,  Linda Pei Ee CHUA

IPC分类号： H01L21/30

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L25/03 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of forming through-hole vias in a semiconductor wafer involves forming a semiconductor wafer with many die having contact pads disposed on each die. The semiconductor wafer has saw street guides between each die. A trench is formed in the saw streets. The trench extends partially but not completely through the wafer. The uncut portion of the saw street guides below the trench along a backside of the wafer maintains structural support for the semiconductor wafer. The trench is filled with organic material. Via holes are formed in the organic material. Traces are formed between the contact pads and via holes. Conductive material is deposited in the via holes to form metal vias. The uncut portion of the saw streets below the trench along the backside of the semiconductor wafer portion is removed. The semiconductor wafer is singulated along the saw street guides to separate the die.

摘要翻译： 在半导体晶片中形成贯通孔的方法包括形成具有多个具有设置在每个管芯上的接触焊盘的管芯的半导体晶片。 半导体晶片在每个管芯之间已经看到了路标。 在锯道上形成一个沟槽。 沟槽部分延伸但不完全穿过晶片。 沿着晶片背面的沟槽下方的锯条引导件的未切割部分保持了半导体晶片的结构支撑。 沟槽充满有机材料。 在有机材料中形成通孔。 在接触垫和通孔之间形成痕迹。 导电材料沉积在通孔中以形成金属通孔。 除去沿着半导体晶片部分的背面的沟槽下方的锯切街道的未切割部分。 半导体晶片沿着锯条导轨分割，以分离模具。

公开(公告)号：US20080272504A1

公开(公告)日：2008-11-06

申请号：US11768825

申请日：2007-06-26

申请人： Byung Tai DO ,  Heap Hoe KUAN ,  Seng Guan CHOW

发明人： Byung Tai DO ,  Heap Hoe KUAN ,  Seng Guan CHOW

IPC分类号： H01L23/544

CPC分类号： H01L23/5384 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/68372 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13138 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06582 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device includes a first die having top, bottom, and peripheral surfaces. A bond pad is formed over the top surface. An organic material is connected to the first die and disposed around the peripheral surface. A via hole is formed in the organic material. A metal trace connects the via hole to the bond pad. A conductive material is deposited in the via hole. A redistribution layer (RDL) has an interconnection pad disposed over the top surface of the first die.

摘要翻译： 半导体器件包括具有顶部，底部和外围表面的第一裸片。 在顶表面上形成接合垫。 有机材料连接到第一模具并围绕周边表面设置。 在有机材料中形成通孔。 金属迹线将通孔连接到接合垫。 导电材料沉积在通孔中。 再分布层（RDL）具有设置在第一管芯的顶表面上的互连焊盘。

公开(公告)号：US20080272464A1

公开(公告)日：2008-11-06

申请号：US11861244

申请日：2007-09-25

申请人： Byung Tai DO ,  Heap Hoe KUAN ,  Linda Pei Ee CHUA

发明人： Byung Tai DO ,  Heap Hoe KUAN ,  Linda Pei Ee CHUA

IPC分类号： H01L23/58 ,  H01L21/30 ,  H01L23/48

CPC分类号： H01L21/6835 ,  H01L21/568 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/12 ,  H01L24/19 ,  H01L24/25 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L25/03 ,  H01L25/0657 ,  H01L2221/68336 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2224/02371 ,  H01L2224/04105 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82001 ,  H01L2225/06513 ,  H01L2225/06551 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor wafer contains a plurality of die with contact pads disposed on a first surface of each die. Metal vias are formed in trenches in the saw street guides and are surrounded by organic material. Traces connect the contact pads and metal vias. The metal vias can be half-circle vias or full-circle vias. The metal vias are surrounded by organic material. Redistribution layers (RDL) are formed on a second surface of the die opposite the first surface. The RDL and THV provide expanded interconnect flexibility to adjacent die. Repassivation layers are formed between the RDL on the second surface of the die for electrical isolation. The die are stackable and can be placed in a semiconductor package with other die. The RDL provide electrical interconnect to the adjacent die. Bond wires and solder bumps also provide electrical connection to the semiconductor die.

摘要翻译： 半导体晶片包含多个具有设置在每个管芯的第一表面上的接触焊盘的管芯。 金属通孔形成在锯条导轨中的沟槽中，并被有机材料包围。 痕迹连接接触垫和金属通孔。 金属通孔可以是半圆形通孔或全圆形通孔。 金属通孔被有机材料包围。 再次分布层（RDL）形成在模具的与第一表面相对的第二表面上。 RDL和THV为相邻裸片提供了扩展的互连灵活性。 在模具的第二表面上的RDL之间形成再钝化层以进行电绝缘。 芯片是可堆叠的并且可以放置在具有其它裸片的半导体封装中。 RDL为相邻的管芯提供电互连。 接合线和焊料凸起还提供与半导体管芯的电连接。