公开(公告)号：US08390118B2

公开(公告)日：2013-03-05

申请号：US12859635

申请日：2010-08-19

申请人： Pang-Chun Lin ,  Chun-Yuan Li ,  Fu-Di Tang ,  Chien-Ping Huang ,  Chun-Chi Ke

发明人： Pang-Chun Lin ,  Chun-Yuan Li ,  Fu-Di Tang ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/85001 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor package having electrical connecting structures includes: a conductive layer having a die pad and traces surrounding the die pad; a chip; bonding wires; an encapsulant with a plurality of cavities having a depth greater than the thickness of the die pad and traces for embedding the die pad and the traces therein, and the cavities exposing the die pad and the traces; a solder mask layer formed in the cavities and having a plurality of openings for exposing the trace ends and a portion of the die pad; and solder balls formed in the openings and electrically connected to the trace ends. Engaging the solder mask layer with the encapsulant enhances adhesion strength of the solder mask layer so as to prolong the moisture permeation path and enhance package reliability.

摘要翻译： 具有电连接结构的半导体封装包括：具有管芯焊盘和围绕管芯焊盘的迹线的导电层; 一个芯片 接合线; 具有多个空腔的密封剂，其深度大于管芯焊盘的厚度，以及用于将管芯焊盘和其中的迹线嵌入其中的迹线，以及使裸片焊盘和迹线露出的空腔; 形成在所述空腔中的焊料掩模层，并且具有用于暴露所述迹线端部和所述管芯焊盘的一部分的多个开口; 以及形成在开口中并电连接到迹线端的焊球。 将焊料掩模层与密封剂接合，增强了焊料掩模层的粘合强度，从而延长了水分渗透路径并提高了封装的可靠性。

公开(公告)号：US20120241937A1

公开(公告)日：2012-09-27

申请号：US13492220

申请日：2012-06-08

申请人： Chang-Yueh Chan ,  Chien-Ping Huang ,  Chun-Chi Ke ,  Chun-An Huang ,  Chih-Ming Huang

发明人： Chang-Yueh Chan ,  Chien-Ping Huang ,  Chun-Chi Ke ,  Chun-An Huang ,  Chih-Ming Huang

IPC分类号： H01L23/498

CPC分类号： H01L21/02 ,  B81B7/007 ,  B81B2207/07 ,  H01L23/52 ,  H01L29/84 ,  H01L2224/02166 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

摘要： Proposed is a package structure having a micro-electromechanical (MEMS) element, including a chip having a plurality of electrical connecting pads and a MEMS element formed thereon; a lid disposed on the chip for covering the MEMS element; a stud bump disposed on each of the electrical connecting pads; an encapsulant formed on the chip with part of the stud bumps being exposed from the encapsulant; and a metal conductive layer formed on the encapsulant and connected to the stud bumps. The invention is characterized by completing the packaging process on the wafer directly to enable thinner and cheaper package structures to be fabricated within less time. This invention further provides a method for fabricating the package structure as described above.

摘要翻译： 提出具有微机电（MEMS）元件的封装结构，其包括具有多个电连接焊盘和形成在其上的MEMS元件的芯片; 设置在所述芯片上用于覆盖所述MEMS元件的盖; 设置在每个电连接焊盘上的螺柱凸块; 形成在芯片上的密封剂，其中一部分柱状凸块从密封剂暴露出来; 以及金属导电层，形成在密封剂上并连接到凸块上。 本发明的特征在于直接完成晶片上的封装工艺，以便在更短的时间内制造更薄和更便宜的封装结构。 本发明还提供如上所述的用于制造封装结构的方法。

公开(公告)号：US08253248B2

公开(公告)日：2012-08-28

申请号：US12956393

申请日：2010-11-30

申请人： Chun-Chi Ke ,  Chien-Ping Huang

发明人： Chun-Chi Ke ,  Chien-Ping Huang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/013

摘要： A semiconductor device having conductive bumps and a fabrication method thereof is proposed. The fabrication method includes the steps of forming a first metallic layer on a substrate having solder pads and a passivation layer formed thereon, and electrically connecting it to the solder pads; applying a second covering layer over exposed parts of the first metallic layer; subsequently, forming a second metallic layer on the second covering layer, and electrically connecting it to the exposed parts of the first metallic layer; applying a third covering layer, and forming openings for exposing parts of the second metallic layer to form thereon a conductive bump having a metallic standoff and a solder material. The covering layers and the metallic layers can provide a buffering effect for effectively absorbing the thermal stress imposed on the conductive bumps to prevent delamination caused by the UBM layers.

摘要翻译： 提出了具有导电凸块的半导体器件及其制造方法。 该制造方法包括以下步骤：在具有焊盘和形成在其上的钝化层的基板上形成第一金属层，并将其电连接到焊盘; 在第一金属层的暴露部分上施加第二覆盖层; 随后在第二覆盖层上形成第二金属层，并将其电连接到第一金属层的暴露部分; 施加第三覆盖层，以及形成用于暴露第二金属层的部分的开口以在其上形成具有金属支座和焊料材料的导电凸块。 覆盖层和金属层可以提供缓冲效果，用于有效地吸收施加在导电凸块上的热应力，以防止由UBM层引起的分层。

公开(公告)号：US20120038044A1

公开(公告)日：2012-02-16

申请号：US12959148

申请日：2010-12-02

申请人： Chiang-Cheng Chang ,  Chien-Ping Huang ,  Chun-Chi Ke ,  Hsin-Yi Liao ,  Hsi-Chang Hsu

发明人： Chiang-Cheng Chang ,  Chien-Ping Huang ,  Chun-Chi Ke ,  Hsin-Yi Liao ,  Hsi-Chang Hsu

IPC分类号： H01L23/488 ,  H01L21/44

CPC分类号： H01L24/82 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/32 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2224/24225 ,  H01L2224/25171 ,  H01L2224/32155 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/3511

摘要： A CSP includes: a hard board having a first wiring layer with conductive pads; a plurality of conductive elements disposed on at least a portion of the conductive pads; an electronic component having opposite active and inactive surfaces and being mounted on the hard board via the inactive surface; an encapsulating layer disposed on the hard board for encapsulating the conductive elements and electronic component, the active surface of the electronic component and the surfaces of the conductive elements being exposed through the encapsulating layer; a first dielectric layer and a third wiring layer disposed on the encapsulating layer, the third wiring layer being electrically connected to the conductive elements and the electronic component and further electrically connected to the first wiring layer through the conductive elements, thereby obtaining a stacked connection structure without the need of PTHs and using the hard board as a main structure to avoid warpage.

摘要翻译： CSP包括：具有带导电焊盘的第一布线层的硬板; 布置在所述导电垫的至少一部分上的多个导电元件; 电子元件具有相反的有源和无效表面，并且经由非活性表面安装在硬板上; 设置在所述硬板上用于封装所述导电元件和电子部件的封装层，所述电子部件的所述有源表面和所述导电元件的表面通过所述封装层露出; 设置在所述封装层上的第一电介质层和第三布线层，所述第三布线层电连接到所述导电元件和所述电子部件，并且还通过所述导电元件与所述第一布线层电连接，从而获得堆叠连接结构 不需要PTH和使用硬板作为主要结构，以避免翘曲。

公开(公告)号：US20120007234A1

公开(公告)日：2012-01-12

申请号：US12967839

申请日：2010-12-14

申请人： Yueh-Ying Tsai ,  Fu-Di Tang ,  Chien-Ping Huang ,  Chun-Chi Ke

发明人： Yueh-Ying Tsai ,  Fu-Di Tang ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC分类号： H01L23/48 ,  H01L21/56

CPC分类号： H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/3142 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/73265 ,  H01L2224/81395 ,  H01L2224/81439 ,  H01L2224/83395 ,  H01L2224/83439 ,  H01L2224/85001 ,  H01L2224/85395 ,  H01L2224/85439 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package without a chip carrier formed thereon and a fabrication method thereof. A metallic carrier is half-etched to form a plurality of grooves and metal studs corresponding to the grooves. The grooves are filled with a first encapsulant and a plurality of bonding pads are formed on the metal studs. The first encapsulant is bonded with the metal studs directly. Each of the bonding pads and one of the metal studs corresponding to the bonding pad form a T-shaped structure. Therefore, bonding force between the metal studs and the first encapsulant is enhanced such that delamination is avoided. Die mounting, wire-bonding and molding processes are performed subsequently. Since the half-etched grooves are filled with the first encapsulant, the drawback of having pliable metallic carrier that makes transportation difficult to carry out as encountered in prior techniques is overcome, and the manufacturing cost is educed by not requiring the use of costly metals as an etching resist layer.

摘要翻译： 其上形成有芯片载体的半导体封装及其制造方法。 金属载体被半蚀刻以形成对应于凹槽的多个凹槽和金属螺柱。 凹槽填充有第一密封剂，并且在金属螺柱上形成多个接合焊盘。 第一密封剂直接与金属螺栓结合。 每个接合焊盘和对应于接合焊盘的一个金属螺柱形成T形结构。 因此，金属螺柱和第一密封剂之间的结合力增强，从而避免分层。 随后进行模具安装，引线接合和成型工艺。 由于半蚀刻槽被第一密封剂填充，因此克服了使现有技术中遇到的导致难以进行运输的柔韧金属载体的缺陷，并且通过不需要使用昂贵的金属来促进制造成本 抗蚀剂层。

公开(公告)号：US20120001328A1

公开(公告)日：2012-01-05

申请号：US12967844

申请日：2010-12-14

申请人： Chiang-Cheng Chang ,  Chien-Ping Huang ,  Chun-Chi Ke

发明人： Chiang-Cheng Chang ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC分类号： H01L23/498 ,  H01L21/78

CPC分类号： H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

摘要： A chip-sized package and a fabrication method thereof are provided. The method includes forming a protection layer on an active surface of a chip and attaching a non-active surface of the chip to a carrier made of a hard material; performing a molding process and removing a protection layer from the chip; performing an RDL process to prevent problems as encountered in the prior art, such as softening of adhesive films, an encapsulant overflow, a pliable chip and chip deviation or contamination caused by directly adhering the active surface of the chip to the adhesive film that may even lead to inferior electrical contacts between a circuit layer and a plurality of chip bond pads during subsequent RDL process, and cause the package to be scraped. Further, the carrier employed in this invention can be repetitively used in the process to help reduce manufacturing costs.

摘要翻译： 提供了一种芯片尺寸的封装及其制造方法。 该方法包括在芯片的有源表面上形成保护层，并将芯片的非活性表面附着到由硬质材料制成的载体上; 执行模制过程并从芯片去除保护层; 执行RDL处理以防止现有技术中遇到的问题，例如粘合剂膜的软化，密封剂溢出，柔韧的芯片和芯片偏差或由将芯片的活性表面直接粘附到甚至可能粘合的粘合剂膜引起的污染 在随后的RDL处理期间导致电路层和多个芯片接合焊盘之间的较差的电接触，并导致封装被刮除。 此外，本发明中使用的载体可以在该过程中重复使用以帮助降低制造成本。

公开(公告)号：US20110227226A1

公开(公告)日：2011-09-22

申请号：US13151823

申请日：2011-06-02

申请人： Chiang-Cheng Chiang ,  Chien-Ping Huang ,  Chin-Huang Chang ,  Chi-Hsin Chiu ,  Jung-Pin Huang

发明人： Chiang-Cheng Chiang ,  Chien-Ping Huang ,  Chin-Huang Chang ,  Chi-Hsin Chiu ,  Jung-Pin Huang

IPC分类号： H01L23/48

CPC分类号： H01L29/0657 ,  H01L23/481 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/14181 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/05599

摘要： The invention discloses a multi-chip stack structure having through silicon via and a method for fabricating the same. The method includes: providing a wafer having a plurality of first chips; forming a plurality of holes on a first surface of each of the first chips and forming metal posts and solder pads corresponding to the holes so as to form a through silicon via (TSV) structure; forming at least one groove on a second surface of each of the first chips to expose the metal posts of the TSV structure so as to allow at least one second chip to be stacked on the first chip, received in the groove and electrically connected to the metal posts exposed from the groove; filling the groove with an insulating material for encapsulating the second chip; mounting conductive elements on the solder pads of the first surface of each of the first chips and singulating the wafer; and mounting and electrically connecting the stacked first and second chips to a chip carrier via the conductive elements. The wafer, which is not totally thinned but includes a plurality of first chips, severs a carrying purpose during the fabrication process and thereby solves problems, namely a complicated process, high cost, and adhesive layer contamination, facing the prior art that entails repeated use of a carrier board and an adhesive layer for vertically stacking a plurality of chips and mounting the stacked chips on a chip carrier.

摘要翻译： 本发明公开了一种通过硅通孔的多芯片堆叠结构及其制造方法。 该方法包括：提供具有多个第一芯片的晶片; 在每个所述第一芯片的第一表面上形成多个孔，并形成对应于所述孔的金属柱和焊盘，以形成贯穿硅通孔（TSV）结构; 在所述第一芯片的每一个的第二表面上形成至少一个凹槽以暴露所述TSV结构的所述金属柱，以允许至少一个第二芯片堆叠在所述第一芯片上，被接收在所述凹槽中并电连接到 从槽露出的金属柱; 用绝缘材料填充凹槽以封装第二芯片; 将导电元件安装在每个第一芯片的第一表面的焊盘上并分离晶片; 并且经由导电元件将堆叠的第一和第二芯片安装并电连接到芯片载体。 不是完全变薄但包括多个第一芯片的晶片在制造过程中切断了承载目的，从而解决了面临现有技术需要重复使用的问题，即复杂的工艺，高成本和粘合剂层污染 的载体板和用于垂直堆叠多个芯片的粘合剂层，并将堆叠的芯片安装在芯片载体上。

公开(公告)号：US08013443B2

公开(公告)日：2011-09-06

申请号：US12727307

申请日：2010-03-19

申请人： Fang-Lin Tsai ,  Ho-Yi Tsai ,  Chih-Ming Huang ,  Chien-Ping Huang

发明人： Fang-Lin Tsai ,  Ho-Yi Tsai ,  Chih-Ming Huang ,  Chien-Ping Huang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/3121 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/3025 ,  H05K3/284 ,  H05K3/3442 ,  H05K3/3452 ,  H05K2201/0989 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2924/00

摘要： An electronic carrier board and a package structure thereof are provided. The electronic carrier board includes a carrier, at least one pair of bond pads formed on the carrier, and a protective layer covering the carrier. The protective layer is formed with openings for exposing the bond pads. A groove is formed between the paired bond pads and has a length larger than a width of an electronic component mounted on the paired bond pads. The groove is adjacent to one of the paired bond pads and communicates with a corresponding one of the openings where this bond pad is exposed. Accordingly, a clearance between the electronic component and the electronic carrier board can be effectively filled with an insulating resin for encapsulating the electronic component, thereby preventing voids and undesirable electrical bridging between the paired bond pads from occurrence.

摘要翻译： 提供电子载体板及其封装结构。 电子载板包括载体，形成在载体上的至少一对接合焊盘和覆盖载体的保护层。 保护层形成有用于暴露接合焊盘的开口。 在成对的接合焊盘之间形成有一个沟槽，其长度大于安装在成对接合焊盘上的电子部件的宽度。 该沟槽与一对接合焊盘相邻，并与该接合焊盘露出的相应的一个开口连通。 因此，电子部件和电子载体板之间的间隙可以有效地填充用于封装电子部件的绝缘树脂，从而防止成对焊盘之间的空隙和不期望的电桥发生。

公开(公告)号：US08013436B2

公开(公告)日：2011-09-06

申请号：US12157831

申请日：2008-06-13

申请人： Min-Shun Hung ,  Yo-Yi Tsai ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

发明人： Min-Shun Hung ,  Yo-Yi Tsai ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

IPC分类号： H01L23/34

CPC分类号： H01L23/4334 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2224/0401 ,  H01L2224/45099

摘要： A heat dissipation package structure and method for fabricating the same are disclosed, which includes mounting and electrically connecting a semiconductor chip to a chip carrier through its active surface; mounting a heat dissipation member having a heat dissipation section and a supporting section on the chip carrier such that the semiconductor chip can be received in the space formed by the heat dissipation section and the supporting section, wherein the heat dissipation section has an opening formed corresponding to the semiconductor chip; forming an encapsulant to encapsulate the semiconductor chip and the heat dissipation member; and thinning the encapsulant to remove the encapsulant formed on the semiconductor chip to expose inactive surface of the semiconductor chip and the top surface of the heat dissipation section from the encapsulant. Therefore, the heat dissipation package structure is fabricated through simplified fabrication steps at low cost, and also the problem that the chip is easily damaged in a package molding process of the prior art is overcome.

摘要翻译： 公开了一种散热封装结构及其制造方法，其包括通过其有源表面安装和电连接半导体芯片到芯片载体; 将具有散热部和支撑部的散热部件安装在所述芯片载体上，使得所述半导体芯片能够容纳在由所述散热部和所述支撑部形成的空间中，其中，所述散热部具有相应形成的开口 到半导体芯片; 形成密封剂以封装半导体芯片和散热构件; 并且使所述密封剂变薄以除去形成在所述半导体芯片上的所述密封剂，以从所述密封剂暴露所述半导体芯片的无效表面和所述散热部分的顶表面。 因此，通过以低成本的简化的制造步骤制造散热封装结构，并且克服了在现有技术的封装成型工艺中芯片容易损坏的问题。

公开(公告)号：US07985618B2

公开(公告)日：2011-07-26

申请号：US13023185

申请日：2011-02-08

申请人： Yun-Lung Tsai ,  Yu-Chieh Tsai ,  Chien-Chih Chen ,  Chien-Ping Huang

发明人： Yun-Lung Tsai ,  Yu-Chieh Tsai ,  Chien-Chih Chen ,  Chien-Ping Huang

IPC分类号： H01L21/00

CPC分类号： H01L25/18 ,  H01L21/565 ,  H01L23/04 ,  H01L23/3121 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/15162 ,  H01L2924/181 ,  H01L2924/19105 ,  H05K3/284 ,  H05K2201/09127 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A semiconductor device and a fabrication method thereof are provided. An opening having at least one slanted side is formed on a substrate. At least one chip and at least one passive component are mounted on the substrate. An encapsulant having a cutaway corner is formed on the substrate to encapsulate the chip and the passive component, wherein the cutaway corner of the encapsulant is spaced apart from the slanted side of the opening by a predetermined distance. A singulation process is performed to cut the encapsulant to form a package with a chamfer. The package is embedded in a lid to form the semiconductor device, wherein a portion of the substrate located between the slanted side of the opening and the cutaway corner of the encapsulant is exposed from the encapsulant to form an exposed portion. The present invention also provides a carrier for the semiconductor device.