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公开(公告)号:US09854671B1
公开(公告)日:2017-12-26
申请号:US15410745
申请日:2017-01-19
发明人: Wei-Ti Lin , Chun-Hsien Chien , Yu-Chung Hsieh , Yu-Hua Chen
CPC分类号: H05K1/115 , H01F17/0013 , H01F17/0033 , H01F27/24 , H01F27/2804 , H01F2017/002 , H01F2027/2809 , H05K1/036 , H05K1/0366 , H05K1/165 , H05K3/4076 , H05K3/42 , H05K3/423 , H05K3/426 , H05K3/4644 , H05K2201/0187 , H05K2201/0195 , H05K2201/086 , H05K2201/0959
摘要: A circuit board includes a substrate, a first magnetic structure, a first dielectric layer and an inductive coil. The substrate has a top surface and a bottom surface. The first magnetic structure is disposed on the top surface of the substrate. The first dielectric layer covers the substrate and the first magnetic structure. The inductive coil includes a first interconnect, a second interconnect and a plurality of conductive pillars. The first interconnect is disposed on the first dielectric layer. The second interconnect is disposed on the bottom surface of the substrate. The conductive pillars connect the first interconnect and the second interconnect. The first interconnect, the second interconnect and the conductive pillars form a helical structure surrounding the first magnetic structure.
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公开(公告)号:US09806050B2
公开(公告)日:2017-10-31
申请号:US14742672
申请日:2015-06-17
发明人: Pao-Hung Chou , Chih-Hao Hsu
IPC分类号: H05K3/36 , H01L23/00 , H01L21/56 , H01L21/683 , H01L23/31
CPC分类号: H01L24/19 , H01L21/568 , H01L21/6835 , H01L23/3128 , H01L24/20 , H01L24/83 , H01L2221/68372 , H01L2224/12105 , H01L2224/24227 , H01L2224/92244 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/15153 , H01L2924/1517 , H01L2924/15747 , H01L2924/18162 , Y10T29/49126 , H01L2924/00
摘要: A package structure includes: a first dielectric layer having a first surface and a second surface opposing the first surface; a semiconductor chip embedded in the first dielectric layer in a manner that the semiconductor chip protrudes from the second surface, and having an active surface and an inactive surface opposing the active surface, electrode pads being disposed on the active surface and in the first dielectric layer, the inactive surface and a part of a side surface adjacent the inactive surface protruding from the second surface; a first circuit layer disposed on the first surface; a built-up structure disposed on the first surface and the first circuit layer; and an insulating protective layer disposed on the built-up structure, a plurality of cavities being formed in the insulating protective layer for exposing a part of a surface of the built-up structure. The package structure includes only one built-up structure.
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公开(公告)号:US20170273189A1
公开(公告)日:2017-09-21
申请号:US15252247
申请日:2016-08-31
发明人: Shih-Lian Cheng
CPC分类号: H05K3/064 , G03F7/0002 , G03F7/162 , G03F7/20 , H05K1/115 , H05K3/0023 , H05K3/06 , H05K3/108 , H05K3/4644 , H05K3/465 , H05K2201/091 , H05K2203/0108 , H05K2203/0369 , H05K2203/0502 , H05K2203/0548 , H05K2203/0562 , Y10T29/49124
摘要: A manufacturing method of a circuit board and a piezochromic stamp are provided. A circuit pattern is formed on a dielectric substrate. A dielectric layer having a hole or a conductive via and covering the circuit pattern is formed on the dielectric substrate. A conductive seed layer is formed on the dielectric layer. A photoresist layer is formed on the conductive seed layer. A piezochromic stamp is imprinted on the photoresist layer, wherein when the pressing side of the piezochromic stamp is in contact with the conductive seed layer, the light transmittance effect thereof is changed to blocking or allowing light having a specific wavelength to pass through. A patterned photoresist layer is formed by using the piezochromic stamp as a mask. A patterned metal layer is formed on the exposed conductive seed layer. The patterned photoresist layer and the conductive seed layer are removed.
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公开(公告)号:US20170223841A1
公开(公告)日:2017-08-03
申请号:US15488519
申请日:2017-04-17
发明人: Chun-Ting Lin
IPC分类号: H05K3/40 , H01L21/677 , H01L21/67 , H01L21/673 , H05K1/11
摘要: A carrier substrate includes a circuit structure layer, a first solder resist layer, a second solder resist layer and conductive towers. The circuit structure layer includes a core structure layer, a first circuit layer and a second circuit layer. The first solder resist layer has first openings exposing a portion of the first circuit layer. The second solder resist layer has second openings exposing a portion of the second circuit layer. The conductive towers are disposed at the first openings, higher than a surface of the first solder resist layer and connected with the first openings exposed by the first circuit layer, wherein a diameter of each of the conductive towers gradually increases by a direction from away-from the first openings towards close-to the first openings. A diameter of the second conductive towers is greater than that of the first conductive towers.
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公开(公告)号:US09691699B2
公开(公告)日:2017-06-27
申请号:US14931808
申请日:2015-11-03
发明人: Chia-Chan Chang , Gwo-Chaur Chen , Yung-Tsai Chen
IPC分类号: H05K3/10 , H01L23/498 , H01L21/48
CPC分类号: H05K1/09 , H01L21/4846 , H01L21/4875 , H01L23/49811 , H01L23/49827 , H01L23/49838 , H01L23/49866 , H01L2224/16227 , H01L2224/81005 , H01L2924/1531 , H01L2924/3511 , H05K1/181 , H05K3/007 , H05K3/188 , H05K3/3436 , H05K2201/10674 , H05K2201/10734 , Y02P70/613
摘要: A method for manufacturing a circuit structure is described as follows. Two patterned circuit layers are formed on a core layer. The patterned circuit layers are located on two opposite surfaces of the core layer. A patterned insulating layer is respectively formed on each of the patterned circuit layers. The patterned insulating layers respectively expose a portion of the patterned circuit layers. The core layer is removed so as to expose an upper surface of each of the patterned circuit layers and a top surface of each of the patterned insulating layers. The upper surface of each of the patterned circuit layers is aligned with the top surface of each of the patterned insulating layers.
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公开(公告)号:US20170171975A1
公开(公告)日:2017-06-15
申请号:US15426062
申请日:2017-02-07
发明人: Shu-Sheng Chiang , Ming-Hao Wu , Wei-Ming Cheng
CPC分类号: H05K1/111 , H05K1/0266 , H05K1/0296 , H05K1/0298 , H05K1/09 , H05K1/115 , H05K3/0047 , H05K3/0073 , H05K3/4038 , H05K3/4092 , H05K3/4644 , H05K3/4697 , H05K2201/09036 , H05K2201/094 , H05K2201/09563 , H05K2201/09781 , H05K2203/0376 , H05K2203/163
摘要: A circuit board structure includes an inner circuit structure and a first build-up circuit structure. The inner circuit structure includes a core layer having an upper surface and a lower surface, a first patterned circuit layer disposed on the upper surface, a second patterned circuit layer disposed on the lower surface and a conductive through hole connecting the first and the second patterned circuit layers. The first build-up circuit structure at least has a cavity and an inner dielectric layer. The inner dielectric layer has an opening connecting the cavity and exposing a portion of the first patterned circuit layer. A hole diameter of the opening is smaller than a hole diameter of cavity. A height difference is between an inner surface of the inner dielectric layer exposed by the cavity and a top surface of the first patterned circuit layer exposed by the opening.
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公开(公告)号:US20170171973A1
公开(公告)日:2017-06-15
申请号:US15287718
申请日:2016-10-06
发明人: Ming-Hao Wu , Shu-Sheng Chiang , Wei-Ming Cheng
CPC分类号: H05K1/111 , H05K1/0266 , H05K1/0296 , H05K1/0298 , H05K1/09 , H05K1/115 , H05K3/0047 , H05K3/0073 , H05K3/4038 , H05K3/4092 , H05K3/4644 , H05K3/4697 , H05K2201/09036 , H05K2201/094 , H05K2201/09563 , H05K2201/09781 , H05K2203/0376 , H05K2203/163
摘要: A circuit board structure includes an inner circuit structure and a first build-up circuit structure. The inner circuit structure includes a core layer having an upper surface and a lower surface, a first patterned circuit layer disposed on the upper surface, a second patterned circuit layer disposed on the lower surface and a conductive through hole connecting the first and the second patterned circuit layers. The first build-up circuit structure at least has a cavity and an inner dielectric layer. The inner dielectric layer has an opening communicating the cavity and a pad of the first patterned circuit layer is located in the opening. A hole diameter of the opening is smaller than a hole diameter of cavity. An inner surface of the inner dielectric layer exposed by the cavity and a top surface of the pad are coplanar or have a height difference.
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公开(公告)号:US20170164468A1
公开(公告)日:2017-06-08
申请号:US14997583
申请日:2016-01-18
发明人: HUNG-LIN CHANG , MING-HAO WU , SYUN-SIAO CHANG , CHENG-PO YU , CHI-MIN CHANG
CPC分类号: H05K3/4697 , H05K3/4644
摘要: A manufacturing method of a circuit board structure is described as follows. An inner circuit structure including a core layer having an upper and an opposite lower surface, a first patterned circuit layer disposed on the upper surface and a second patterned circuit layer disposed on the lower surface is provided. An insulating material layer is formed on a portion of the first patterned circuit layer. A laser resisting layer is formed on at least a portion of the insulating material layer. A release layer is adhered to the laser resisting layer. A build-up process is performed so as to laminate a first and a second build-up circuit structures on the first and the second patterned circuit layers, respectively. A laser ablation process is performed on the first build-up circuit structure so as to form a cavity at least exposing a portion of the upper surface of the core layer.
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公开(公告)号:US09581774B2
公开(公告)日:2017-02-28
申请号:US15164878
申请日:2016-05-26
发明人: Yin-Ju Chen , Cheng-Po Yu , Pei-Chang Huang
IPC分类号: G02B6/43 , G02B6/42 , H01L31/0232 , G02B6/12 , G02B6/32
CPC分类号: G02B6/428 , G02B6/12004 , G02B6/32 , G02B6/4206 , G02B6/4244 , G02B6/4245 , G02B6/4274 , G02B6/43 , H01L31/0232 , H01L31/02327 , H01L31/167
摘要: An optical component including a multi-layer substrate, an optical waveguide element, and two optical-electro assemblies is provided. The multi-layer substrate includes a dielectric layer, two circuit layers, and two through holes passing through the dielectric layer. The optical waveguide element is located on the multi-layer substrate and between the through holes. The optical-electro assemblies are respectively inserted into the corresponding through holes and correspondingly located at two opposite ends of the optical waveguide element. One of the optical-electro assemblies transforms an electrical signal into a light beam and provides the light beam to the optical waveguide element, and the other one of the optical-electro assemblies receives the light beam transmitted from the optical waveguide element and transforms the light beam into another electrical signal. A manufacturing method of the optical component and an optical-electro circuit board having the optical component are also provided.
摘要翻译: 提供了包括多层基板,光波导元件和两个光电组件的光学部件。 多层基板包括电介质层,两个电路层和穿过电介质层的两个通孔。 光波导元件位于多层基板上并且位于通孔之间。 光电组件分别插入对应的通孔中并相应地位于光波导元件的两个相对端。 光电组件中的一个将电信号转换成光束并将光束提供给光波导元件,另一个光电组件接收从光波导元件传输的光束并转换光 射入另一个电信号。 还提供了具有光学部件的光学部件的制造方法和光电路板。
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公开(公告)号:US09559045B2
公开(公告)日:2017-01-31
申请号:US14799593
申请日:2015-07-15
发明人: Pi-Te Pan , Chang-Fu Chen
IPC分类号: H01L23/00 , H01L23/36 , H01L23/498 , H01L21/48
CPC分类号: H01L23/49811 , H01L21/486 , H01L23/16 , H01L23/36 , H01L23/3735 , H01L23/49805 , H01L23/49827 , H01L23/5383 , H01L23/5384 , H01L23/562 , H01L24/16 , H01L24/73 , H01L24/81 , H01L25/0655 , H01L25/105 , H01L2224/16227 , H01L2224/16235 , H01L2224/73253 , H01L2225/1058 , H01L2924/15311 , H01L2924/1533 , H01L2924/18161 , H01L2924/3511 , H01L2924/37001
摘要: Provided is a package structure including a circuit board, a plurality of first contact pads, a plurality of metal pillars and at least one chip. The first contact pads are disposed on the circuit board. The chip is disposed on one portion of the first contact pads. The metal pillars are disposed on the other portion of the first contact pads, where the chip is surrounded by the metal pillars. A method for manufacturing the package structure is also provided.
摘要翻译: 提供包括电路板,多个第一接触焊盘,多个金属柱和至少一个芯片的封装结构。 第一接触垫设置在电路板上。 芯片设置在第一接触垫的一部分上。 金属支柱设置在第一接触垫的另一部分上,其中芯片被金属支柱包围。 还提供了一种用于制造封装结构的方法。
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