公开(公告)号：US20180098435A1

公开(公告)日：2018-04-05

申请号：US15820397

申请日：2017-11-21

Applicant: Unimicron Technology Corp.

Inventor： Cheng-Chieh Chiu ,  Chia-Chan Chang ,  Chun-Yi Kuo ,  Yu-Cheng Lin

IPC: H05K3/06 ,  H05K3/46 ,  H05K3/40 ,  H05K1/11

CPC classification number: H05K3/061 ,  H05K1/113 ,  H05K3/4007 ,  H05K3/4038 ,  H05K3/4647 ,  H05K3/4682 ,  H05K2201/096 ,  H05K2203/0502

Abstract: A circuit board element includes a glass substrate, a first dielectric layer, and a first patterned metal layer. The glass substrate has an edge. The first dielectric layer is disposed on the glass substrate and has a central region and an edge region. The edge region is in contact with the edge of the glass substrate, and the thickness of the central region is greater than the thickness of the edge region. The first patterned metal layer is disposed on the glass substrate and in the central region of the first dielectric layer.

公开(公告)号：US09917046B2

公开(公告)日：2018-03-13

申请号：US15201602

申请日：2016-07-04

Applicant: Unimicron Technology Corp.

Inventor： Chien-Te Wu ,  Chien-Tsai Li ,  Cheng-Chung Lo

IPC: H01K3/10 ,  H01L23/498 ,  H01L21/683 ,  H05K1/03 ,  H05K3/00 ,  H05K1/11 ,  H05K3/12 ,  H05K3/40 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6833 ,  H01L23/49822 ,  H01L23/49827 ,  H05K1/0306 ,  H05K1/115 ,  H05K3/002 ,  H05K3/0023 ,  H05K3/0029 ,  H05K3/1275 ,  H05K3/4007 ,  H05K3/4038 ,  Y10T29/49165

Abstract: Provided is a manufacturing method of a circuit board structure including steps as below. A glass film is provided on an electrostatic chuck (E-chuck). A plurality of first conductive vias are formed in the glass film. A first circuit layer is formed on an upper surface of the glass film, such that the first circuit layer is electrically connected with the first conductive vias. A first polymer layer is formed on the first circuit layer. The first polymer layer covers a surface of the first circuit layer and the upper surface of the glass film. A plurality of second conductive vias are formed in the first polymer layer. A second circuit layer is formed on the first polymer layer, such that the second circuit layer is electrically connected with the second conductive vias. The E-chuck is removed.

公开(公告)号：US09916990B2

公开(公告)日：2018-03-13

申请号：US14955053

申请日：2015-12-01

Applicant: Unimicron Technology Corp.

Inventor： Wen-Lung Lai ,  Yuan-Liang Lo

IPC: H01L21/48 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H05K3/00 ,  H05K3/20 ,  H01L23/00

CPC classification number: H01L21/486 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/181 ,  H05K3/0052 ,  H05K3/007 ,  H05K3/0097 ,  H05K3/205 ,  Y10T29/49165 ,  H01L2924/00015 ,  H01L2224/45099 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A packaging substrate includes a holder, a first conductive pad disposed on the holder, a core layer disposed on the holder, a circuit layer disposed on the core layer, a plurality of conductive vias disposed in the core layer, and an insulating protection layer disposed on the core layer, wherein the first electrical pad is embedded in the core layer. By combining the holder on one side of the packaging substrate, cracks due to over-thinness can be prevented during transferring or packaging. A method of fabricating the packaging substrate, a package structure having a holder, a method of fabricating the package structure are also provided.

公开(公告)号：US09854671B1

公开(公告)日：2017-12-26

申请号：US15410745

申请日：2017-01-19

Applicant: Unimicron technology Corp.

Inventor： Wei-Ti Lin ,  Chun-Hsien Chien ,  Yu-Chung Hsieh ,  Yu-Hua Chen

IPC: H05K3/42 ,  H05K1/11 ,  H05K1/16 ,  H05K3/40 ,  H01F27/28 ,  H01F27/24

CPC classification number: H05K1/115 ,  H01F17/0013 ,  H01F17/0033 ,  H01F27/24 ,  H01F27/2804 ,  H01F2017/002 ,  H01F2027/2809 ,  H05K1/036 ,  H05K1/0366 ,  H05K1/165 ,  H05K3/4076 ,  H05K3/42 ,  H05K3/423 ,  H05K3/426 ,  H05K3/4644 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2201/086 ,  H05K2201/0959

Abstract: A circuit board includes a substrate, a first magnetic structure, a first dielectric layer and an inductive coil. The substrate has a top surface and a bottom surface. The first magnetic structure is disposed on the top surface of the substrate. The first dielectric layer covers the substrate and the first magnetic structure. The inductive coil includes a first interconnect, a second interconnect and a plurality of conductive pillars. The first interconnect is disposed on the first dielectric layer. The second interconnect is disposed on the bottom surface of the substrate. The conductive pillars connect the first interconnect and the second interconnect. The first interconnect, the second interconnect and the conductive pillars form a helical structure surrounding the first magnetic structure.

公开(公告)号：US09806050B2

公开(公告)日：2017-10-31

申请号：US14742672

申请日：2015-06-17

Applicant: Unimicron Technology Corp.

Inventor： Pao-Hung Chou ,  Chih-Hao Hsu

IPC: H05K3/36 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31

CPC classification number: H01L24/19 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/20 ,  H01L24/83 ,  H01L2221/68372 ,  H01L2224/12105 ,  H01L2224/24227 ,  H01L2224/92244 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15747 ,  H01L2924/18162 ,  Y10T29/49126 ,  H01L2924/00

Abstract: A package structure includes: a first dielectric layer having a first surface and a second surface opposing the first surface; a semiconductor chip embedded in the first dielectric layer in a manner that the semiconductor chip protrudes from the second surface, and having an active surface and an inactive surface opposing the active surface, electrode pads being disposed on the active surface and in the first dielectric layer, the inactive surface and a part of a side surface adjacent the inactive surface protruding from the second surface; a first circuit layer disposed on the first surface; a built-up structure disposed on the first surface and the first circuit layer; and an insulating protective layer disposed on the built-up structure, a plurality of cavities being formed in the insulating protective layer for exposing a part of a surface of the built-up structure. The package structure includes only one built-up structure.

公开(公告)号：US20170273189A1

公开(公告)日：2017-09-21

申请号：US15252247

申请日：2016-08-31

Applicant: Unimicron Technology Corp.

Inventor： Shih-Lian Cheng

IPC: H05K3/06 ,  H05K3/10

CPC classification number: H05K3/064 ,  G03F7/0002 ,  G03F7/162 ,  G03F7/20 ,  H05K1/115 ,  H05K3/0023 ,  H05K3/06 ,  H05K3/108 ,  H05K3/4644 ,  H05K3/465 ,  H05K2201/091 ,  H05K2203/0108 ,  H05K2203/0369 ,  H05K2203/0502 ,  H05K2203/0548 ,  H05K2203/0562 ,  Y10T29/49124

Abstract: A manufacturing method of a circuit board and a piezochromic stamp are provided. A circuit pattern is formed on a dielectric substrate. A dielectric layer having a hole or a conductive via and covering the circuit pattern is formed on the dielectric substrate. A conductive seed layer is formed on the dielectric layer. A photoresist layer is formed on the conductive seed layer. A piezochromic stamp is imprinted on the photoresist layer, wherein when the pressing side of the piezochromic stamp is in contact with the conductive seed layer, the light transmittance effect thereof is changed to blocking or allowing light having a specific wavelength to pass through. A patterned photoresist layer is formed by using the piezochromic stamp as a mask. A patterned metal layer is formed on the exposed conductive seed layer. The patterned photoresist layer and the conductive seed layer are removed.

公开(公告)号：US20170223841A1

公开(公告)日：2017-08-03

申请号：US15488519

申请日：2017-04-17

Applicant: Unimicron Technology Corp.

Inventor： Chun-Ting Lin

IPC: H05K3/40 ,  H01L21/677 ,  H01L21/67 ,  H01L21/673 ,  H05K1/11

Abstract: A carrier substrate includes a circuit structure layer, a first solder resist layer, a second solder resist layer and conductive towers. The circuit structure layer includes a core structure layer, a first circuit layer and a second circuit layer. The first solder resist layer has first openings exposing a portion of the first circuit layer. The second solder resist layer has second openings exposing a portion of the second circuit layer. The conductive towers are disposed at the first openings, higher than a surface of the first solder resist layer and connected with the first openings exposed by the first circuit layer, wherein a diameter of each of the conductive towers gradually increases by a direction from away-from the first openings towards close-to the first openings. A diameter of the second conductive towers is greater than that of the first conductive towers.

公开(公告)号：US09691699B2

公开(公告)日：2017-06-27

申请号：US14931808

申请日：2015-11-03

Applicant: Unimicron Technology Corp.

Inventor： Chia-Chan Chang ,  Gwo-Chaur Chen ,  Yung-Tsai Chen

IPC: H05K3/10 ,  H01L23/498 ,  H01L21/48

CPC classification number: H05K1/09 ,  H01L21/4846 ,  H01L21/4875 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L2224/16227 ,  H01L2224/81005 ,  H01L2924/1531 ,  H01L2924/3511 ,  H05K1/181 ,  H05K3/007 ,  H05K3/188 ,  H05K3/3436 ,  H05K2201/10674 ,  H05K2201/10734 ,  Y02P70/613

Abstract: A method for manufacturing a circuit structure is described as follows. Two patterned circuit layers are formed on a core layer. The patterned circuit layers are located on two opposite surfaces of the core layer. A patterned insulating layer is respectively formed on each of the patterned circuit layers. The patterned insulating layers respectively expose a portion of the patterned circuit layers. The core layer is removed so as to expose an upper surface of each of the patterned circuit layers and a top surface of each of the patterned insulating layers. The upper surface of each of the patterned circuit layers is aligned with the top surface of each of the patterned insulating layers.

公开(公告)号：US20170171975A1

公开(公告)日：2017-06-15

申请号：US15426062

申请日：2017-02-07

Applicant: Unimicron Technology Corp.

Inventor： Shu-Sheng Chiang ,  Ming-Hao Wu ,  Wei-Ming Cheng

IPC: H05K1/11 ,  H05K3/46 ,  H05K3/00

CPC classification number: H05K1/111 ,  H05K1/0266 ,  H05K1/0296 ,  H05K1/0298 ,  H05K1/09 ,  H05K1/115 ,  H05K3/0047 ,  H05K3/0073 ,  H05K3/4038 ,  H05K3/4092 ,  H05K3/4644 ,  H05K3/4697 ,  H05K2201/09036 ,  H05K2201/094 ,  H05K2201/09563 ,  H05K2201/09781 ,  H05K2203/0376 ,  H05K2203/163

Abstract: A circuit board structure includes an inner circuit structure and a first build-up circuit structure. The inner circuit structure includes a core layer having an upper surface and a lower surface, a first patterned circuit layer disposed on the upper surface, a second patterned circuit layer disposed on the lower surface and a conductive through hole connecting the first and the second patterned circuit layers. The first build-up circuit structure at least has a cavity and an inner dielectric layer. The inner dielectric layer has an opening connecting the cavity and exposing a portion of the first patterned circuit layer. A hole diameter of the opening is smaller than a hole diameter of cavity. A height difference is between an inner surface of the inner dielectric layer exposed by the cavity and a top surface of the first patterned circuit layer exposed by the opening.

公开(公告)号：US20170171973A1

公开(公告)日：2017-06-15

申请号：US15287718

申请日：2016-10-06

Applicant: Unimicron Technology Corp.

Inventor： Ming-Hao Wu ,  Shu-Sheng Chiang ,  Wei-Ming Cheng

IPC: H05K1/11 ,  H05K3/40 ,  H05K1/09 ,  H05K3/46

CPC classification number: H05K1/111 ,  H05K1/0266 ,  H05K1/0296 ,  H05K1/0298 ,  H05K1/09 ,  H05K1/115 ,  H05K3/0047 ,  H05K3/0073 ,  H05K3/4038 ,  H05K3/4092 ,  H05K3/4644 ,  H05K3/4697 ,  H05K2201/09036 ,  H05K2201/094 ,  H05K2201/09563 ,  H05K2201/09781 ,  H05K2203/0376 ,  H05K2203/163

Abstract: A circuit board structure includes an inner circuit structure and a first build-up circuit structure. The inner circuit structure includes a core layer having an upper surface and a lower surface, a first patterned circuit layer disposed on the upper surface, a second patterned circuit layer disposed on the lower surface and a conductive through hole connecting the first and the second patterned circuit layers. The first build-up circuit structure at least has a cavity and an inner dielectric layer. The inner dielectric layer has an opening communicating the cavity and a pad of the first patterned circuit layer is located in the opening. A hole diameter of the opening is smaller than a hole diameter of cavity. An inner surface of the inner dielectric layer exposed by the cavity and a top surface of the pad are coplanar or have a height difference.