公开(公告)号：US09236320B2

公开(公告)日：2016-01-12

申请号：US14315163

申请日：2014-06-25

Applicant: XINTEC INC.

Inventor： Yi-Ming Chang ,  Tsang-Yu Liu ,  Yen-Shih Ho ,  Ying-Nan Wen

IPC: H01L23/31 ,  H01L23/00

CPC classification number: H01L23/3171 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L2224/0231 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05026 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05184 ,  H01L2224/05548 ,  H01L2224/05562 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06155 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/10157 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A chip package is provided. The chip package includes a semiconductor chip, an isolation layer, a redistributing metal layer, and at least a bonding pad. The semiconductor chip includes at least one conducting disposed on a surface of the semiconductor chip. The isolation layer is disposed on the surface of the semiconductor chip, wherein the isolation layer has at least one first opening to expose the first conducting pad. The redistributing metal layer is disposed on the isolation layer and has at least a redistributing metal line corresponding to the conducting pad, the redistributing metal line is connected to the first conducting pad through the first opening. The bonding pad is disposed on the isolation layer and one side of the semiconductor chip, wherein the redistributing metal line extends to the bonding pad to electrically connect the conducting pad to the bonding pad.

Abstract translation: 提供芯片封装。 芯片封装包括半导体芯片，隔离层，再分布金属层和至少一个焊盘。 半导体芯片包括设置在半导体芯片的表面上的至少一个导体。 隔离层设置在半导体芯片的表面上，其中隔离层具有至少一个第一开口以暴露第一导电焊盘。 再分配金属层设置在隔离层上，并且至少具有对应于导电焊盘的再分布金属线，再分布金属线通过第一开口连接到第一导电焊盘。 接合焊盘设置在隔离层和半导体芯片的一侧，其中再分布金属线延伸到接合焊盘，以将导电焊盘电连接到接合焊盘。

公开(公告)号：US09196754B2

公开(公告)日：2015-11-24

申请号：US14516492

申请日：2014-10-16

Applicant: XINTEC INC.

Inventor： Chia-Sheng Lin

IPC: H01L21/70 ,  H01L31/02 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L23/525 ,  H01L27/146 ,  H01L31/0232 ,  H01L31/18 ,  H01L33/58 ,  H01L33/62 ,  H01L23/00

CPC classification number: H01L31/02005 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/525 ,  H01L24/13 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14685 ,  H01L31/02327 ,  H01L31/1876 ,  H01L33/58 ,  H01L33/62 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2924/0001 ,  H01L2924/1461 ,  H01L2933/0058 ,  H01L2933/0066 ,  H01L2224/05599 ,  H01L2224/13099 ,  H01L2924/00

Abstract: A chip package is disclosed. The package includes a semiconductor chip having a first surface and a second surface opposite thereto, at least one conductive pad adjacent to the first surface, and an opening extending toward the first surface from the second surface to expose the conductive pad. The caliber adjacent to the first surface is greater than that of the opening adjacent to the second surface. An insulating layer and a redistribution layer (RDL) are successively disposed on the second surface and extend to a sidewall and a bottom of the opening, in which the RDL is electrically connected to the conductive pad through the opening. A passivation layer covers the RDL and partially fills the opening to form a void between the passivation layer and the conductive pad in the opening. A fabrication method of the chip package is also disclosed.

Abstract translation: 公开了一种芯片封装。 所述封装包括具有第一表面和与其相对的第二表面的半导体芯片，与所述第一表面相邻的至少一个导电焊盘以及从所述第二表面向所述第一表面延伸以露出所述导电焊盘的开口。 与第一表面相邻的口径大于与第二表面相邻的开口的口径。 绝缘层和再分配层（RDL）依次设置在第二表面上并延伸到开口的侧壁和底部，RDL通过开口与导电焊盘电连接。 钝化层覆盖RDL并且部分填充开口以在开口中的钝化层和导电垫之间形成空隙。 还公开了芯片封装的制造方法。

公开(公告)号：US09196571B2

公开(公告)日：2015-11-24

申请号：US14592840

申请日：2015-01-08

Applicant: XINTEC INC.

Inventor： Chia-Sheng Lin ,  Po-Han Lee

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/48 ,  H01L23/538 ,  H01L21/784 ,  H01L23/31 ,  H01L23/00 ,  H01L27/146

CPC classification number: H01L23/481 ,  H01L21/481 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76898 ,  H01L21/78 ,  H01L21/784 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/3192 ,  H01L23/5389 ,  H01L23/564 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/73 ,  H01L24/83 ,  H01L24/94 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14636 ,  H01L27/14687 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/29011 ,  H01L2224/29082 ,  H01L2224/2919 ,  H01L2224/73253 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00014

Abstract: A chip device package and a fabrication method thereof are provided. The chip device package includes a semiconductor substrate having a first surface and an opposing second surface. A recessed portion is disposed adjacent to a sidewall of the semiconductor substrate, extending from the first surface of the semiconductor substrate to at least the second surface of the semiconductor substrate. A protection layer is disposed over the first surface of the semiconductor substrate and in the recessed portion. A through hole is disposed on the first surface of the semiconductor substrate. A buffer material that is different from the material of the protection layer is disposed in the through hole and covered by the protection layer.

Abstract translation: 提供了一种芯片器件封装及其制造方法。 芯片器件封装包括具有第一表面和相对的第二表面的半导体衬底。 凹部与半导体衬底的侧壁相邻地设置，从半导体衬底的第一表面延伸到半导体衬底的至少第二表面。 保护层设置在半导体衬底的第一表面和凹部中。 在半导体衬底的第一表面上设置通孔。 与保护层的材料不同的缓冲材料设置在通孔中并被保护层覆盖。

公开(公告)号：US09190362B2

公开(公告)日：2015-11-17

申请号：US14325812

申请日：2014-07-08

Applicant: XINTEC INC.

Inventor： Wen-Cheng Chien ,  Wen-Ken Huang ,  Chien-Hung Liu ,  Joey Lai

IPC: H01L21/00 ,  H01L23/00 ,  H01L27/146

CPC classification number: H01L23/562 ,  H01L24/05 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2224/02235 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00

Abstract: The invention provides a chip package and a fabrication method thereof. In one embodiment, the chip package includes: a substrate having a semiconductor device and a conductive pad thereon; an insulator ring filling a trench formed in the substrate, wherein the insulator ring surrounds an intermediate layer below the conductive pad; and a conductive layer disposed below a backside of the substrate and electrically connected to the conductive pad.

Abstract translation: 本发明提供一种芯片封装及其制造方法。 在一个实施例中，芯片封装包括：衬底，其上具有半导体器件和导电焊盘; 填充形成在所述衬底中的沟槽的绝缘体环，其中所述绝缘体环围绕所述导电焊盘下方的中间层; 以及设置在所述基板的背面下方并与导电焊盘电连接的导电层。

公开(公告)号：US08993365B2

公开(公告)日：2015-03-31

申请号：US14191348

申请日：2014-02-26

Applicant: Xintec Inc.

Inventor： Yi-Ming Chang ,  Kuo-Hua Liu ,  Yi-Cheng Wang ,  Sheng-Yen Chang

IPC: H01L21/00 ,  H01L31/0203 ,  H01L21/683

CPC classification number: H01L21/6836 ,  H01L21/6835 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/48091 ,  H01L2924/16235 ,  H01L2924/00014

Abstract: A wafer packaging method includes the following steps. A wafer having a plurality of integrated circuit units is provided. A first surface of the wafer opposite to the integrated circuit units is ground. A release layer is formed on a second surface of a light transmissive carrier. An ultraviolet temporary bonding layer is formed on the second surface of the light transmissive carrier or a third surface of the wafer. The ultraviolet temporary bonding layer is used to adhere the second surface of the light transmissive carrier to the third surface of the wafer. The first surface of the wafer is adhered to an ultraviolet tape. A fourth surface of the light transmissive carrier is exposed to ultraviolet to eliminate adhesion force of the ultraviolet temporary bonding layer. The light transmissive carrier and the release layer are removed.

Abstract translation: 晶片封装方法包括以下步骤。 提供具有多个集成电路单元的晶片。 与集成电路单元相对的晶片的第一表面被研磨。 剥离层形成在透光载体的第二表面上。 在透光载体的第二表面或晶片的第三表面上形成紫外线临时粘接层。 紫外线暂时接合层用于将透光载体的第二表面粘附到晶片的第三表面。 晶片的第一表面粘附到紫外线带上。 透光载体的第四表面暴露于紫外线以消除紫外线临时粘合层的粘附力。 去除透光载体和释放层。

公开(公告)号：US08975739B2

公开(公告)日：2015-03-10

申请号：US14152970

申请日：2014-01-10

Applicant: Xintec Inc.

Inventor： Ming-Chung Chung

IPC: H01L23/482 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L21/76885 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3171 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014

Abstract: The invention provides an electronic device package and method for manufacturing thereof. The electronic device package includes a substrate, an electronic chip, a bonding pad, a first passivation layer, a conductive layer, a second passivation layer, and a solder ball. The conductive layer has a first side end and a second side end, and the solder ball is positioned on the first side end of the conductive layer. The second passivation layer contacts with both the upper surface and the sidewall of the second side end of the conductive layer, and the first passivation layer contacts with the lower surface of the second side end of the conductive layer, so as to completely encapsulate the second end of the conductive layer. The electronic device package accordingly prevents the moisture penetration and to enhance the reliability of the electronic device.

Abstract translation: 本发明提供一种电子器件封装及其制造方法。 电子器件封装包括衬底，电子芯片，焊盘，第一钝化层，导电层，第二钝化层和焊球。 导电层具有第一侧端和第二侧端，并且焊球位于导电层的第一侧端。 第二钝化层与导电层的第二侧端的上表面和侧壁接触，并且第一钝化层与导电层的第二侧端的下表面接触，以便完全封装第二钝化层 导电层的端部。 因此，电子装置封装防止了水分渗透并提高了电子设备的可靠性。

公开(公告)号：US08963312B2

公开(公告)日：2015-02-24

申请号：US14339341

申请日：2014-07-23

Applicant: Xintec Inc.

Inventor： Yen-Shih Ho ,  Tsang-Yu Liu ,  Shu-Ming Chang ,  Yu-Lung Huang ,  Chao-Yen Lin ,  Wei-Luen Suen ,  Chien-Hui Chen

IPC: H01L23/02 ,  H01L23/48 ,  H01L21/44 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/49 ,  G06K9/00053 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/02381 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/06135 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/43 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48599 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48669 ,  H01L2224/48687 ,  H01L2224/4869 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/146 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A stacked chip package including a device substrate having an upper surface, a lower surface and a sidewall is provided. The device substrate includes a sensing region or device region, a signal pad region and a shallow recess structure extending from the upper surface toward the lower surface along the sidewall. A redistribution layer is electrically connected to the signal pad region and extends into the shallow recess structure. A wire has a first end disposed in the shallow recess structure and electrically connected to the redistribution layer, and a second end electrically connected to a first substrate and/or a second substrate disposed under the lower surface. A method for forming the stacked chip package is also provided.

Abstract translation: 提供了包括具有上表面，下表面和侧壁的器件衬底的堆叠芯片封装。 器件衬底包括感测区域或器件区域，信号焊盘区域和沿着侧壁从上表面向下表面延伸的浅凹陷结构。 再分配层电连接到信号焊盘区域并延伸到浅凹陷结构中。 电线具有设置在浅凹陷结构中并电连接到再分布层的第一端，以及电连接到设置在下表面下方的第一基板和/或第二基板的第二端。 还提供了一种用于形成堆叠芯片封装的方法。

公开(公告)号：US08952501B2

公开(公告)日：2015-02-10

申请号：US13950101

申请日：2013-07-24

Applicant: Xintec Inc.

Inventor： Yu-Lung Huang ,  Chao-Yen Lin ,  Wei-Luen Suen ,  Chien-Hui Chen

IPC: H01L29/06 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/683

CPC classification number: H01L23/49805 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3121 ,  H01L24/05 ,  H01L24/16 ,  H01L24/48 ,  H01L24/95 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having an upper surface and a lower surface; a device region or sensing region defined in the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; at least two recesses extending from the upper surface towards the lower surface of the semiconductor substrate, wherein sidewalls and bottoms of the recesses together form a sidewall of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to the sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：具有上表面和下表面的半导体衬底; 限定在所述半导体衬底中的器件区域或感测区域; 导电焊盘，位于所述半导体衬底的上表面上; 至少两个从所述半导体衬底的上表面向下表面延伸的凹槽，其中所述凹槽的侧壁和底部一起形成所述半导体衬底的侧壁; 导电层，电连接到导电焊盘并从半导体衬底的上表面延伸到半导体衬底的侧壁; 以及位于导电层和半导体衬底之间的绝缘层。

公开(公告)号：US08928098B2

公开(公告)日：2015-01-06

申请号：US13714218

申请日：2012-12-13

Applicant: Xintec Inc.

Inventor： Hung-Jen Lee ,  Shu-Ming Chang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/007 ,  B81C1/0023 ,  B81C1/00301

Abstract: A semiconductor package includes: a chip having a first portion and a second portion disposed on the first portion, wherein the second portion has at least a through hole therein for exposing a portion of the first portion, and the first portion and/or the second portion has a MEMS; and an etch stop layer formed between the first portion and the second portion and partially exposed through the through hole of the second portion. The invention allows an electronic element to be received in the through hole so as for the semiconductor package to have integrated functions of the MEMS and the electronic element. Therefore, the need to dispose the electronic element on a circuit board as in the prior art can be eliminated, thereby saving space on the circuit board.

Abstract translation: 半导体封装包括：具有第一部分和设置在第一部分上的第二部分的芯片，其中第二部分至少在其中具有用于暴露第一部分的一部分的通孔，以及第一部分和/或第二部分 部分具有MEMS; 以及形成在所述第一部分和所述第二部分之间并且部分地暴露于所述第二部分的通孔的蚀刻停止层。 本发明允许电子元件被容纳在通孔中，以便半导体封装具有MEMS和电子元件的集成功能。 因此，可以消除如现有技术那样将电子元件配置在电路板上，从而节省了电路板上的空间。

公开(公告)号：US20140306343A1

公开(公告)日：2014-10-16

申请号：US14251470

申请日：2014-04-11

Applicant: XINTEC INC.

Inventor： Yu-Lung HUANG ,  Shu-Ming CHANG ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/78

CPC classification number: H01L24/14 ,  H01L21/78 ,  H01L22/12 ,  H01L22/20 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/11334 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/14131 ,  H01L2224/14145 ,  H01L2224/14177 ,  H01L2224/14179 ,  H01L2224/16058 ,  H01L2224/16227 ,  H01L2224/17051 ,  H01L2224/17517 ,  H01L2224/17519 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/14146 ,  H01L2224/81 ,  H01L2224/81907 ,  H01L2924/00012 ,  H01L2224/11

Abstract: A chip package is provided, in which includes: a packaging substrate, a chip and a plurality solder balls interposed between the packaging substrate and the chip for bonding the packaging substrate and the chip, wherein the solder balls include a first portion of a first size and a second portion of a second size that is different from the first size.

Abstract translation: 提供了一种芯片封装，其中包括：封装基板，芯片和介于封装基板和芯片之间的多个焊球，用于接合封装基板和芯片，其中焊球包括第一尺寸的第一部分 以及与第一尺寸不同的第二尺寸的第二部分。