公开(公告)号：US08294279B2

公开(公告)日：2012-10-23

申请号：US11307127

申请日：2006-01-24

申请人： Ke-Hung Chen ,  Shih-Hsiung Lin ,  Mou-Shiung Lin

发明人： Ke-Hung Chen ,  Shih-Hsiung Lin ,  Mou-Shiung Lin

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L25/0657 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49575 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/26145 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81193 ,  H01L2224/83051 ,  H01L2224/83365 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01007 ,  H01L2924/01083 ,  H01L2924/00012 ,  H01L2224/29099

摘要： A method of assembling chips. A first chip and a second chip are provided. At least one conductive pillar is formed on the first chip, and a conductive connecting material is formed on the conductive pillar. The second chip also comprises at least one conductive pillar. The first chip is connected to the second chip via the conductive pillars and the conductive connecting material.

摘要翻译： 一种组装芯片的方法。 提供第一芯片和第二芯片。 在第一芯片上形成至少一个导电柱，并且在导电柱上形成导电连接材料。 第二芯片还包括至少一个导电柱。 第一芯片经由导电柱和导电连接材料连接到第二芯片。

公开(公告)号：US08044475B2

公开(公告)日：2011-10-25

申请号：US12353250

申请日：2009-01-13

申请人： Mou-Shiung Lin ,  Shih-Hsiung Lin ,  Hsin-Jung Lo

发明人： Mou-Shiung Lin ,  Shih-Hsiung Lin ,  Hsin-Jung Lo

IPC分类号： H01L29/78

CPC分类号： H01L31/0203 ,  H01L27/14618 ,  H01L27/14683 ,  H01L27/14687 ,  H01L31/18 ,  H01L2224/48091 ,  H01L2924/00014

摘要： A chip package includes a bump connecting said semiconductor chip and said circuitry component, wherein the semiconductor chip has a photosensitive area used to sense light. The chip package may include a ring-shaped protrusion connecting a transparent substrate and the semiconductor chip.

摘要翻译： 芯片封装包括连接所述半导体芯片和所述电路部件的凸块，其中所述半导体芯片具有用于感测光的感光区域。 芯片封装可以包括连接透明基板和半导体芯片的环形突起。

公开(公告)号：US07973401B2

公开(公告)日：2011-07-05

申请号：US12269045

申请日：2008-11-12

申请人： Mou-Shiung Lin ,  Shih-Hsiung Lin ,  Hsin-Jung Lo ,  Ying-Chih Chen ,  Chiu-Ming Chou

发明人： Mou-Shiung Lin ,  Shih-Hsiung Lin ,  Hsin-Jung Lo ,  Ying-Chih Chen ,  Chiu-Ming Chou

IPC分类号： H01L23/02 ,  H01L23/48

CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L23/525 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/49 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06558 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A chip package comprises a first chip having a first side and a second side, wherein said first chip comprises a first pad, a first trace, a second pad and a first passivation layer at said first side thereof, an opening in said first passivation layer exposing said first pad, said first trace being over said first passivation layer, said first trace connecting said first pad to said second pad; a second chip having a first side and a second side, wherein said second chip comprises a first pad at said first side thereof, wherein said second side of said second chip is joined with said second side of side first chip; a substrate joined with said first side of said first chip or with said first side of said second chip; a first wirebonding wire connecting said second pad of said first chip and said substrate; and a second wirebonding wire connecting said first pad of said second chip and said substrate.

摘要翻译： 芯片封装包括具有第一侧和第二侧的第一芯片，其中所述第一芯片包括第一焊盘，第一焊盘，第二焊盘和在其第一侧的第一钝化层，所述第一钝化层中的开口 暴露所述第一焊盘，所述第一迹线在所述第一钝化层之上，所述第一迹线将所述第一焊盘连接到所述第二焊盘; 具有第一侧和第二侧的第二芯片，其中所述第二芯片包括在其第一侧的第一焊盘，其中所述第二芯片的所述第二侧与所述第二芯片的所述第二侧接合; 与所述第一芯片的所述第一侧或所述第二芯片的所述第一侧连接的衬底; 连接所述第一芯片的所述第二焊盘和所述衬底的第一引线接合线; 以及连接所述第二芯片的所述第一焊盘和所述衬底的第二引线键合线。

公开(公告)号：US07968372B2

公开(公告)日：2011-06-28

申请号：US12128644

申请日：2008-05-29

申请人： Shih-Hsiung Lin ,  Mou-Shiung Lin

发明人： Shih-Hsiung Lin ,  Mou-Shiung Lin

IPC分类号： H01L21/00 ,  H01L23/48 ,  H05K7/00

摘要： A copper pillar may be provided on a chip and a first tin-containing layer may be provided over the copper pillar. A second tin-containing layer may be provided on a substrate. The first tin-containing layer may be joined with the second tin-containing layer during a packaging process.

公开(公告)号：US20090121302A1

公开(公告)日：2009-05-14

申请号：US12353250

申请日：2009-01-13

申请人： Mou-Shiung Lin ,  Shih-Hsiung Lin ,  Hsin-Jung Lo

发明人： Mou-Shiung Lin ,  Shih-Hsiung Lin ,  Hsin-Jung Lo

IPC分类号： H01L23/00 ,  H01L23/48 ,  H01L23/02 ,  H01L27/14 ,  H01L23/485

CPC分类号： H01L31/0203 ,  H01L27/14618 ,  H01L27/14683 ,  H01L27/14687 ,  H01L31/18 ,  H01L2224/48091 ,  H01L2924/00014

摘要： A chip package includes a bump connecting said semiconductor chip and said circuitry component, wherein the semiconductor chip has a photosensitive area used to sense light. The chip package may include a ring-shaped protrusion connecting a transparent substrate and the semiconductor chip.

摘要翻译： 芯片封装包括连接所述半导体芯片和所述电路部件的凸块，其中所述半导体芯片具有用于感测光的感光区域。 芯片封装可以包括连接透明基板和半导体芯片的环形突起。

公开(公告)号：US20090057900A1

公开(公告)日：2009-03-05

申请号：US12269045

申请日：2008-11-12

申请人： Mou-Shiung Lin ,  Shih-Hsiung Lin ,  Hsin-Jung Lo ,  Ying-Chih Chen ,  Chiu-Ming Chou

发明人： Mou-Shiung Lin ,  Shih-Hsiung Lin ,  Hsin-Jung Lo ,  Ying-Chih Chen ,  Chiu-Ming Chou

IPC分类号： H01L23/49

CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L23/525 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/49 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06558 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A chip package comprises a first chip having a first side and a second side, wherein said first chip comprises a first pad, a first trace, a second pad and a first passivation layer at said first side thereof, an opening in said first passivation layer exposing said first pad, said first trace being over said first passivation layer, said first trace connecting said first pad to said second pad; a second chip having a first side and a second side, wherein said second chip comprises a first pad at said first side thereof, wherein said second side of said second chip is joined with said second side of side first chip; a substrate joined with said first side of said first chip or with said first side of said second chip; a first wirebonding wire connecting said second pad of said first chip and said substrate; and a second wirebonding wire connecting said first pad of said second chip and said substrate.

摘要翻译： 芯片封装包括具有第一侧和第二侧的第一芯片，其中所述第一芯片包括第一焊盘，第一焊盘，第二焊盘和在其第一侧的第一钝化层，所述第一钝化层中的开口 暴露所述第一焊盘，所述第一迹线在所述第一钝化层之上，所述第一迹线将所述第一焊盘连接到所述第二焊盘; 具有第一侧和第二侧的第二芯片，其中所述第二芯片包括在其第一侧的第一焊盘，其中所述第二芯片的所述第二侧与所述第二芯片的所述第二侧接合; 与所述第一芯片的所述第一侧或所述第二芯片的所述第一侧连接的衬底; 连接所述第一芯片的所述第二焊盘和所述衬底的第一引线接合线; 以及连接所述第二芯片的所述第一焊盘和所述衬底的第二引线键合线。

公开(公告)号：US20080296761A1

公开(公告)日：2008-12-04

申请号：US12132628

申请日：2008-06-04

申请人： Jin-Yuan Lee ,  Chien-Kang Chou ,  Shih-Hsiung Lin ,  Hsi-Shan Kuo

发明人： Jin-Yuan Lee ,  Chien-Kang Chou ,  Shih-Hsiung Lin ,  Hsi-Shan Kuo

IPC分类号： H01L23/485 ,  H01L21/60

CPC分类号： H01L25/0657 ,  H01L24/11 ,  H01L24/13 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05672 ,  H01L2224/05684 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/11849 ,  H01L2224/11906 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13099 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13123 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13609 ,  H01L2224/16145 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2225/06513 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/013

摘要： A cylindrical bonding structure and its method of manufacture. The cylindrical bonding structure is formed over the bonding pad of a silicon chip and the chip is flipped over to connect with a substrate board in the process of forming a flip-chip package. The cylindrical bonding structure mainly includes a conductive cylinder and a solder block. The conductive cylinder is formed over the bonding pad of the silicon chip and the solder block is attached to the upper end of the conductive cylinder. The solder block has a melting point lower than the conductive cylinder. The solder block can be configured into a cylindrical, spherical or hemispherical shape. To fabricate the cylindrical bonding structure, a patterned mask layer having a plurality of openings that correspond in position to the bonding pads on the wafer is formed over a silicon wafer. Conductive material is deposited into the openings to form conductive cylinders and finally a solder block is attached to the end of each conductive cylinder.

摘要翻译： 圆柱形粘结结构及其制造方法。 在硅芯片的接合焊盘上形成圆柱形接合结构，并且在形成倒装芯片封装的过程中将芯片翻转以与衬底板连接。 圆柱形接合结构主要包括导电圆柱体和焊料块。 导电圆柱体形成在硅芯片的接合焊盘上，并且焊接块附接到导电圆柱体的上端。 焊料块的熔点低于导电圆柱体。 焊料块可以配置成圆柱形，球形或半球形。 为了制造圆柱形接合结构，在硅晶片上形成具有与位于晶片上的接合焊盘相对应的多个开口的图案化掩模层。 将导电材料沉积到开口中以形成导电圆柱体，最后在每个导电圆柱体的末端附着焊块。

公开(公告)号：US20080131981A1

公开(公告)日：2008-06-05

申请号：US11950358

申请日：2007-12-04

申请人： Shih-Hsiung Lin ,  Po-Jui Chen ,  Jian-Hong Liu

发明人： Shih-Hsiung Lin ,  Po-Jui Chen ,  Jian-Hong Liu

IPC分类号： H01L21/66

CPC分类号： H01L22/22

摘要： A method for fabricating and testing a semiconductor wafer includes sputtering a TiW layer on a passivation layer and on pads, next sputtering a seed layer, made of gold, on the TiW layer, next forming a photoresist layer on the seed layer, next electroplating gold bumps on the seed layer exposed by openings in the photoresist layer, next removing the photoresist layer, next removing the seed layer not under the gold bumps, next etching the TiW layer not under the gold bumps with an etchant containing H2O2 at a temperature of between 35 and 50 degrees C, or with an etchant containing H2O2 and with ultrasonic waves applied to the etchant, next contacting probe tips of a probe card with some of the gold bumps, next cleaning the probe tips until repeating the step of contacting the probe tips with some of the gold bumps at greater than 100 times, and then after cleaning the probe tips, repeating the step of contacting the probe tips with some of the gold bumps.

摘要翻译： 一种用于制造和测试半导体晶片的方法包括在钝化层和焊盘上溅射TiW层，接下来在TiW层上溅射由金构成的晶种层，接着在种子层上形成光致抗蚀剂层，接下来的电镀金 在光致抗蚀剂层中由开口暴露的晶种层上的突起，接下来去除光致抗蚀剂层，接下来除去不在金凸块之下的种子层，接着用含有H 2的蚀刻剂蚀刻不在金凸块之下的TiW层， 在35至50℃的温度下，或用含有H 2 O 2 O 2的蚀刻剂和超声波 应用于蚀刻剂，接下来将探针卡的探针尖端与一些金凸块接触，然后清洁探针尖端，直到重复将探针尖端与一些金凸块接触大于100次的步骤，然后清洁 探针尖端，重复探针尖端与其中一些接触的步骤 金块。

公开(公告)号：US07242099B2

公开(公告)日：2007-07-10

申请号：US10695630

申请日：2003-10-27

申请人： Shih-Hsiung Lin ,  Mou-Shiung Lin

发明人： Shih-Hsiung Lin ,  Mou-Shiung Lin

IPC分类号： H01L29/40 ,  H01L23/52 ,  H01L23/48 ,  H05K3/24 ,  H05K3/32

CPC分类号： H01L24/11 ,  H01L21/568 ,  H01L21/6835 ,  H01L24/03 ,  H01L24/05 ,  H01L24/12 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05568 ,  H01L2224/05599 ,  H01L2224/1132 ,  H01L2224/1147 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13609 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/731 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2224/83102 ,  H01L2224/85399 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/01082 ,  H01L2224/13099 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

摘要： A method of assembling chips. A first chip and a second chip are provided. At least one conductive pillar is formed on the first chip, and a conductive connecting material is formed on the conductive pillar. The second chip also comprises at least one conductive pillar. The first chip is connected to the second chip via the conductive pillars and the conductive connecting material.

摘要翻译： 一种组装芯片的方法。 提供第一芯片和第二芯片。 在第一芯片上形成至少一个导电柱，并且在导电柱上形成导电连接材料。 第二芯片还包括至少一个导电柱。 第一芯片经由导电柱和导电连接材料连接到第二芯片。

公开(公告)号：US20060261459A1

公开(公告)日：2006-11-23

申请号：US11416134

申请日：2006-05-03

申请人： Mou-Shiung Lin ,  Shih-Hsiung Lin ,  Hsin-Jung Lo ,  Ying-Chih Chen ,  Chiu-Ming Chou

发明人： Mou-Shiung Lin ,  Shih-Hsiung Lin ,  Hsin-Jung Lo ,  Ying-Chih Chen ,  Chiu-Ming Chou

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L23/525 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/49 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06558 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A chip package comprises a first chip having a first side and a second side, wherein said first chip comprises a first pad, a first trace, a second pad and a first passivation layer at said first side thereof, an opening in said first passivation layer exposing said first pad, said first trace being over said first passivation layer, said first trace connecting said first pad to said second pad; a second chip having a first side and a second side, wherein said second chip comprises a first pad at said first side thereof, wherein said second side of said second chip is joined with said second side of side first chip; a substrate joined with said first side of said first chip or with said first side of said second chip; a first wirebonding wire connecting said second pad of said first chip and said substrate; and a second wirebonding wire connecting said first pad of said second chip and said substrate.