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公开(公告)号：US20240365559A1
公开(公告)日：2024-10-31
申请号：US18766899
申请日：2024-07-09
发明人： Bo-Feng Young , Sai-Hooi Yeong , Chi On Chui , Yu-Ming Lin
IPC分类号： H10B51/30 , H01L21/02 , H01L21/768 , H01L29/06 , H01L29/24 , H01L29/423 , H01L29/66 , H01L29/78 , H01L29/786 , H10B43/20 , H10B43/30 , H10B51/20 , H10B99/00
CPC分类号： H10B51/30 , H01L21/02565 , H01L21/02603 , H01L21/76816 , H01L21/76877 , H01L29/0673 , H01L29/24 , H01L29/42392 , H01L29/66969 , H01L29/78391 , H01L29/78696 , H10B43/20 , H10B43/30 , H10B51/20 , H10B99/00
摘要： 3D-NOR memory array devices and methods of manufacture are disclosed herein. A method includes forming a multi-layer stack over a substrate by forming alternating layers of an isolation material and a dummy material. An array of dummy nanostructures is formed in a channel region of the multi-layer stack by performing a wire release process. Once the nanostructures have been formed, a single layer of an oxide semiconductor material is deposited over and surrounds the dummy nanostructures. A memory film is then deposited over the oxide semiconductor material and a conductive wrap-around structure is formed over the memory film. Source/bit line structures may be formed by replacing the layers of the dummy material outside of the channel region with a metal fill material. A staircase conductor structure can be formed the source/bit line structures in a region of the multi-layer stack adjacent the memory array.
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2.发明公开公开(公告)号：US20240365557A1
公开(公告)日：2024-10-31
申请号：US18770406
申请日：2024-07-11
发明人： Sai-Hooi Yeong , Bo-Feng Young , Yu-Ming Lin , Chi On Chui
CPC分类号： H10B51/20 , H01L29/40111 , H01L29/78391 , H01L29/785 , H01L29/78696 , H10B51/00 , H10B51/10 , H10B51/30
摘要： A device includes a first channel; a second channel above the first channel; and a gate structure surrounding the first and second channels, wherein the gate structure includes a ferroelectric (FE) layer surrounding the first and second channels and a gate metal layer surrounding the FE layer. The device further includes two first electrodes connected to two sides of the first channel; two second electrodes connected to two sides of the second channel; a dielectric layer between the first and the second electrodes; and an inner spacer layer between the two first electrodes and the gate structure.
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公开(公告)号：US20240363791A1
公开(公告)日：2024-10-31
申请号：US18766336
申请日：2024-07-08
发明人： Chih Wei Sung , Chung-Bin Tseng , Keng-Ying Liao , Yen-Jou Wu , Po-Zen Chen , Su-Yu Yeh , Ching-Chung Su
IPC分类号： H01L31/18 , H01L23/544 , H01L27/146
CPC分类号： H01L31/1876 , H01L23/544 , H01L27/14621 , H01L27/14627 , H01L27/14636 , H01L27/1464 , H01L27/14683 , H01L27/14687 , H01L31/186 , H01L31/1888 , H01L2223/54426
摘要： A method includes forming image sensors in a semiconductor substrate. A first alignment mark is formed close to a front side of the semiconductor substrate. The method further includes performing a backside polishing process to thin the semiconductor substrate, forming a second alignment mark on the backside of the semiconductor substrate, and forming a feature on the backside of the semiconductor substrate. The feature is formed using the second alignment mark for alignment.
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公开(公告)号：US20240363636A1
公开(公告)日：2024-10-31
申请号：US18768702
申请日：2024-07-10
发明人： Shahaji B. More
IPC分类号： H01L27/092 , H01L21/8234 , H01L29/06 , H01L29/08 , H01L29/66 , H01L29/78
CPC分类号： H01L27/0924 , H01L21/823431 , H01L21/823468 , H01L29/0649 , H01L29/0847 , H01L29/6656 , H01L29/66795 , H01L29/7851
摘要： A method includes forming isolation regions extending into a semiconductor substrate, forming a plurality of semiconductor fins protruding higher than top surfaces of the isolation regions, forming a gate stack on the plurality of semiconductor fins, forming a gate spacer on a sidewall of the gate stack, and recessing the plurality of semiconductor fins to form a plurality of recesses on a side of the gate stack. The plurality of recesses extend to a level lower than top surfaces of the isolation regions. Epitaxy processes are performed to grow an epitaxy region, wherein the epitaxy region fills the plurality of recesses.
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公开(公告)号：US20240363627A1
公开(公告)日：2024-10-31
申请号：US18767022
申请日：2024-07-09
发明人： Kuan-Chang Chiu , Chia-Ching Lee , Chien-Hao Chen , Hung-Chin Chung , Hsien-Ming Lee , Chi On Chui , Hsuan-Yu Tung , Chung-Chiang Wu
IPC分类号： H01L27/088 , H01L21/8234 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/78
CPC分类号： H01L27/0886 , H01L21/823431 , H01L29/41791 , H01L29/42372 , H01L29/6681 , H01L29/785
摘要： A structure includes a semiconductor substrate including a first semiconductor region and a second semiconductor region, a first transistor in the first semiconductor region, and a second transistor in the second semiconductor region. The first transistor includes a first gate dielectric over the first semiconductor region, a first work function layer over and contacting the first gate dielectric, and a first conductive region over the first work function layer. The second transistor includes a second gate dielectric over the second semiconductor region, a second work function layer over and contacting the second gate dielectric, wherein the first work function layer and the second work function layer have different work functions, and a second conductive region over the second work function layer.
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6.发明公开公开(公告)号：US20240363621A1
公开(公告)日：2024-10-31
申请号：US18770552
申请日：2024-07-11
发明人： Yu-Hung YEH , Wun-Jie LIN , Jam-Wem LEE
IPC分类号： H01L27/02 , H01L23/522 , H01L23/535 , H02H9/04
CPC分类号： H01L27/0288 , H01L23/5223 , H01L23/5228 , H01L23/535 , H01L27/0285 , H01L27/0292 , H02H9/046
摘要： An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: a plurality of transistors patterned on a semiconductor substrate during a front-end-of-line (FEOL) process, metal interconnects formed on top of the plurality of transistors during a back-end-of-line (BEOL) process and configured to interconnect the plurality of transistors, and a plurality of passive components formed under the semiconductor substrate in a backside layer during a backside a back-end-of-line (B-BEOL) process, wherein the plurality of passive components are connected to the plurality of transistors through a plurality of vias.
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公开(公告)号：US20240363591A1
公开(公告)日：2024-10-31
申请号：US18767600
申请日：2024-07-09
发明人： Chen-Hua Yu , Chi-Hui Lai , Tin-Hao Kuo , Hao-Yi Tsai , Chung-Shi Liu
IPC分类号： H01L25/065 , H01L21/56 , H01L23/31 , H01L23/367 , H01L23/40
CPC分类号： H01L25/0657 , H01L21/56 , H01L23/3114 , H01L23/367 , H01L23/4006
摘要： An embodiment includes a first package component including a first integrated circuit die and a first encapsulant at least partially surrounding the first integrated circuit die. The device also includes a redistribution structure on the first encapsulant and coupled to the first integrated circuit die. The device also includes a first thermal module coupled to the first integrated circuit die. The device also includes a second package component bonded to the first package component, the second package component including a power module attached to the first package component, the power module including active devices. The device also includes a second thermal module coupled to the power module. The device also includes a mechanical brace extending from a top surface of the second thermal module to a bottom surface of the first thermal module, the mechanical brace physically contacting the first thermal module and the second thermal module.
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公开(公告)号：US20240363563A1
公开(公告)日：2024-10-31
申请号：US18766279
申请日：2024-07-08
发明人： Hung-Shu Huang , Ming-Chyi Liu
IPC分类号： H01L23/00 , H01L23/31 , H01L23/495 , H01L23/498 , H01L23/532
CPC分类号： H01L24/05 , H01L23/3171 , H01L23/4952 , H01L23/49866 , H01L23/53295 , H01L24/03 , H01L2224/04042 , H01L2224/0558 , H01L2224/05686
摘要： A method includes depositing a first dielectric layer covering an electrical connector, depositing a second dielectric layer over the first dielectric layer, and performing a first etching process to etch-through the second dielectric layer and the first dielectric layer. An opening is formed in the first dielectric layer and the second dielectric layer to reveal the electrical connector. A second etching process is performed to laterally etch the first dielectric layer and the second dielectric layer. An isolation layer is deposited to extend into the opening. The isolation layer has a vertical portion and a first horizontal portion in the opening, and a second horizontal portion overlapping the second dielectric layer. An anisotropic etching process is performed on the isolation layer, with the vertical portion of the isolation layer being left in the opening.
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公开(公告)号：US20240363442A1
公开(公告)日：2024-10-31
申请号：US18770052
申请日：2024-07-11
IPC分类号： H01L21/8238 , H01L21/02 , H01L21/28 , H01L21/8234 , H01L27/092 , H01L29/08 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/66 , H01L29/78
CPC分类号： H01L21/823857 , H01L21/02148 , H01L21/02164 , H01L21/02181 , H01L21/02192 , H01L21/28088 , H01L21/823821 , H01L27/0922 , H01L27/0924 , H01L29/0847 , H01L29/42364 , H01L29/4966 , H01L29/511 , H01L29/513 , H01L29/66545 , H01L29/66636 , H01L29/66795 , H01L21/02271 , H01L21/0228 , H01L21/28194 , H01L21/823418 , H01L29/517 , H01L29/6656 , H01L29/7848
摘要： A method includes forming a gate stack of a transistor. The formation of the gate stack includes forming a silicon oxide layer on a semiconductor region, depositing a hafnium oxide layer over the silicon oxide layer, depositing a lanthanum oxide layer over the hafnium oxide layer, and depositing a work-function layer over the lanthanum oxide layer. Source/drain regions are formed on opposite sides of the gate stack.
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公开(公告)号：US20240363440A1
公开(公告)日：2024-10-31
申请号：US18771068
申请日：2024-07-12
发明人： Pei-Hsun Wang , Shih-Cheng Chen , Chun-Hsiung Lin , Chih-Hao Wang
IPC分类号： H01L21/8238 , H01L21/306 , H01L21/3065 , H01L27/092
CPC分类号： H01L21/823821 , H01L21/823814 , H01L27/0924 , H01L21/30604 , H01L21/3065
摘要： A method includes forming an epitaxy semiconductor layer over a semiconductor substrate, and etching the epitaxy semiconductor layer and the semiconductor substrate to form a semiconductor strip, which includes an upper portion acting as a mandrel, and a lower portion under the mandrel. The upper portion is a remaining portion of the epitaxy semiconductor layer, and the lower portion is a remaining portion of the semiconductor substrate. The method further includes growing a first semiconductor fin starting from a first sidewall of the mandrel, growing a second semiconductor fin starting from a second sidewall of the mandrel. The first sidewall and the second sidewall are opposite sidewalls of the mandrel. A first transistor is formed based on the first semiconductor fin. A second transistor is formed based on the second semiconductor fin.
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