公开(公告)号：US20130187268A1

公开(公告)日：2013-07-25

申请号：US13357379

申请日：2012-01-24

Applicant: Chun-Cheng Lin ,  Chung-Shi Liu ,  Kuei-Wei Huang ,  Cheng-Ting Chen ,  Wei-Hung Lin ,  Ming-Da Cheng

Inventor： Chun-Cheng Lin ,  Chung-Shi Liu ,  Kuei-Wei Huang ,  Cheng-Ting Chen ,  Wei-Hung Lin ,  Ming-Da Cheng

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/0273 ,  H01L21/486 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/0239 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/1131 ,  H01L2224/11424 ,  H01L2224/1152 ,  H01L2224/1162 ,  H01L2224/11825 ,  H01L2224/11849 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13611 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01048 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15747 ,  H01L2924/18161 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.

Abstract translation: 提供一种用于封装半导体管芯的系统和方法。 实施例包括具有第一触点和第二触点的第一封装。 在第一接触件上形成接触后材料，以便调节接触垫之间的接头的高度，导体凸块。 在另一个实施例中，使用导电柱来控制接触垫和外部连接之间的接头的高度。

公开(公告)号：US08440503B1

公开(公告)日：2013-05-14

申请号：US13298056

申请日：2011-11-16

Applicant: Hsiu-Jen Lin ,  Chih-Wei Lin ,  Cheng-Ting Chen ,  Ming-Da Cheng ,  Chung-Shi Liu

Inventor： Hsiu-Jen Lin ,  Chih-Wei Lin ,  Cheng-Ting Chen ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L21/00

CPC classification number: H01L24/75 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/75283 ,  H01L2224/7598 ,  H01L2224/81005 ,  H01L2224/81136 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/8123 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/81

Abstract: A method includes placing a cover over a lower package component, wherein the cover comprises an opening aligned to the lower package component. An upper package component is placed over the lower package component. The upper package component is aligned to the opening, and a solder region is dispose between the upper package component and the lower package component. The cover and the upper package component are exposed to a radiation to reflow the solder region.

Abstract translation: 一种方法包括将盖子放置在下部封装部件上，其中盖子包括与下部封装部件对准的开口。 上封装组件放置在下封装组件上。 上部封装部件与开口对准，并且焊接区域配置在上部封装部件和下部封装部件之间。 盖和上部封装部件暴露于辐射以回流焊接区域。

公开(公告)号：US09412689B2

公开(公告)日：2016-08-09

申请号：US13357379

申请日：2012-01-24

Applicant: Chun-Cheng Lin ,  Chung-Shi Liu ,  Kuei-Wei Huang ,  Cheng-Ting Chen ,  Wei-Hung Lin ,  Ming-Da Cheng

Inventor： Chun-Cheng Lin ,  Chung-Shi Liu ,  Kuei-Wei Huang ,  Cheng-Ting Chen ,  Wei-Hung Lin ,  Ming-Da Cheng

IPC: H01L23/02 ,  H01L23/498 ,  H01L25/10 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/0273 ,  H01L21/486 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/0239 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/1131 ,  H01L2224/11424 ,  H01L2224/1152 ,  H01L2224/1162 ,  H01L2224/11825 ,  H01L2224/11849 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13611 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01048 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15747 ,  H01L2924/18161 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.

Abstract translation: 提供一种用于封装半导体管芯的系统和方法。 实施例包括具有第一触点和第二触点的第一封装。 在第一接触件上形成接触后材料，以便调节接触垫之间的接头的高度，导体凸块。 在另一个实施例中，使用导电柱来控制接触垫和外部连接之间的接头的高度。

公开(公告)号：US20130122652A1

公开(公告)日：2013-05-16

申请号：US13298056

申请日：2011-11-16

Applicant: Hsiu-Jen Lin ,  Chih-Wei Lin ,  Cheng-Ting Chen ,  Ming-Da Cheng ,  Chung-Shi Liu

Inventor： Hsiu-Jen Lin ,  Chih-Wei Lin ,  Cheng-Ting Chen ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L21/50

CPC classification number: H01L24/75 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/75283 ,  H01L2224/7598 ,  H01L2224/81005 ,  H01L2224/81136 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/8123 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/81

Abstract: A method includes placing a cover over a lower package component, wherein the cover comprises an opening aligned to the lower package component. An upper package component is placed over the lower package component. The upper package component is aligned to the opening, and a solder region is dispose between the upper package component and the lower package component. The cover and the upper package component are exposed to a radiation to reflow the solder region.

Abstract translation: 一种方法包括将盖子放置在下部封装部件上，其中盖子包括与下部封装部件对准的开口。 上封装组件放置在下封装组件上。 上部封装部件与开口对准，并且焊接区域配置在上部封装部件和下部封装部件之间。 盖和上部封装部件暴露于辐射以回流焊接区域。

公开(公告)号：US20110309490A1

公开(公告)日：2011-12-22

申请号：US12818890

申请日：2010-06-18

Applicant: Chen-Fa Lu ,  Chung-Shi Liu ,  Chen-Hua Yu ,  Wei-Yu Chen ,  Cheng-Ting Chen

Inventor： Chen-Fa Lu ,  Chung-Shi Liu ,  Chen-Hua Yu ,  Wei-Yu Chen ,  Cheng-Ting Chen

IPC: H01L23/498 ,  H01L21/60

CPC classification number: H01L24/13 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0362 ,  H01L2224/03831 ,  H01L2224/03901 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/1147 ,  H01L2224/11622 ,  H01L2224/1181 ,  H01L2224/1183 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/93 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H05K3/28 ,  H05K3/3478 ,  H05K3/4007 ,  H01L2224/11 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/1082

Abstract: A semiconductor device having a polymer layer and a method of fabricating the same is provided. A two-step plasma treatment for a surface of the polymer layer includes a first plasma process to roughen the surface of the polymer layer and loosen contaminants, and a second plasma process to make the polymer layer smoother or make the polymer layer less rough. An etch process may be used between the first plasma process and the second plasma process to remove the contaminants loosened by the first plasma process. In an embodiment, the polymer layer exhibits a surface roughness between about 1% and about 8% as measured by Atomic Force Microscopy (AFM) with the index of surface area difference percentage (SADP) and/or has surface contaminants of less than about 1% of Ti, less than about 1% of F, less than about 1.5% Sn, and less than about 0.4% of Pb.

Abstract translation: 提供了具有聚合物层的半导体器件及其制造方法。 用于聚合物层表面的两步等离子体处理包括使聚合物层的表面粗糙化并且使污染物松动的第一等离子体工艺，以及使聚合物层更平滑或使聚合物层变得粗糙的第二等离子体工艺。 可以在第一等离子体工艺和第二等离子体工艺之间使用蚀刻工艺，以除去由第一等离子体工艺松动的污染物。 在一个实施方案中，聚合物层通过原子力显微镜（AFM）测量的表面粗糙度在约1％至约8％之间，其表面积差异百分比（SADP）指数和/或具有小于约1的表面污染物 的Ti％，小于约1％的F，小于约1.5％的Sn和小于约0.4％的Pb。

公开(公告)号：US06692985B2

公开(公告)日：2004-02-17

申请号：US10163432

申请日：2002-06-07

Applicant: Chorng-Jye Huang ,  Lee Ching Kuo ,  Jyi Tyan Yeh ,  Chien Sheng Huang ,  Leo C. K. Liau ,  Shih-Chen Lin ,  Cheng-Ting Chen ,  Feng-Cheng Jeng

Inventor： Chorng-Jye Huang ,  Lee Ching Kuo ,  Jyi Tyan Yeh ,  Chien Sheng Huang ,  Leo C. K. Liau ,  Shih-Chen Lin ,  Cheng-Ting Chen ,  Feng-Cheng Jeng

IPC: H01L3118

CPC classification number: H01L31/03921 ,  H01L31/03682 ,  H01L31/068 ,  H01L31/075 ,  H01L31/182 ,  Y02E10/546 ,  Y02E10/547 ,  Y02E10/548 ,  Y02P70/521

Abstract: A solar cell substrate with thin film polysilicon. The solar cell substrate includes a substrate; a transparent conductive layer, formed on the substrate; a thermal isolation layer having inlaid conductive layers, formed on the transparent conductive layer; and a polysilicon layer, formed on the thermal isolation layer.

Abstract translation: 具有薄膜多晶硅的太阳能电池基板。 太阳能电池基板包括基板; 形成在基板上的透明导电层; 形成在所述透明导电层上的具有镶嵌导电层的热隔离层; 和形成在热隔离层上的多晶硅层。

公开(公告)号：US06277667B1

公开(公告)日：2001-08-21

申请号：US09391257

申请日：1999-09-07

Applicant: Chorng-Jye Huang ,  Cheng-Ting Chen ,  Chien-sheng Huang ,  Lee-Ching Kuo

Inventor： Chorng-Jye Huang ,  Cheng-Ting Chen ,  Chien-sheng Huang ,  Lee-Ching Kuo

IPC: H01L2100

CPC classification number: H01L31/022425 ,  H01L31/18 ,  Y02E10/50

Abstract: This invention discloses a novel method for fabricating solar cells. Using the existing screen-printing, masking or photolithography techniques, a P-type or N-type diffusion source is coated on the sites of an N-type or P-type silicon wafer desired for forming electrodes. Then, a low dose P-type or N-type diffusion source is in situ diffused into the N-type or P-type silicon wafer together with the P-type or N-type diffusion source coated on the N-type or P-type silicon wafer in the furnace. Thereafter, a P−/P+ or N−/N+ diffusion region is formed within the N-type or P-type silicon wafer. Finally, electrodes aligned to the P+ or N+ diffusion region are formed by means of screen-printing. Then, a solar cell with high photocurrent and low series resistance can be obtained.

Abstract translation: 本发明公开了一种制造太阳能电池的新方法。 使用现有的丝网印刷，掩模或光刻技术，在形成电极所需的N型或P型硅晶片的位置上涂覆P型或N型扩散源。 然后，将低剂量P型或N型扩散源原位扩散到N型或P型硅晶片以及涂覆在N型或P-型硅晶片上的P型或N型扩散源， 在炉中形成硅晶片。 此后，在N型或P型硅晶片内形成P- / P +或N- / N +扩散区。 最后，通过丝网印刷形成与P +或N +扩散区对准的电极。 然后，可以获得具有高光电流和低串联电阻的太阳能电池。

公开(公告)号：US09768137B2

公开(公告)日：2017-09-19

申请号：US13460412

申请日：2012-04-30

Applicant: Meng-Tse Chen ,  Hsiu-Jen Lin ,  Chih-Wei Lin ,  Cheng-Ting Chen ,  Ming-Da Cheng ,  Chung-Shi Liu

Inventor： Meng-Tse Chen ,  Hsiu-Jen Lin ,  Chih-Wei Lin ,  Cheng-Ting Chen ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/10 ,  H01L21/48 ,  H01L23/367

CPC classification number: H01L24/14 ,  H01L21/4853 ,  H01L23/3677 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/1134 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2225/0651 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package structure comprises a substrate, a die bonded to the substrate, and one or more stud bump structures connecting the die to the substrate, wherein each of the stud bump structures having a stud bump and a solder ball encapsulating the stud bump to enhance thermal dissipation and reduce high stress concentrations in the semiconductor package structure.

公开(公告)号：US09538582B2

公开(公告)日：2017-01-03

申请号：US13559318

申请日：2012-07-26

Applicant: Ming-Da Cheng ,  Hsiu-Jen Lin ,  Cheng-Ting Chen ,  Wei-Yu Chen ,  Chien-Wei Lee ,  Chung-Shi Liu

Inventor： Ming-Da Cheng ,  Hsiu-Jen Lin ,  Cheng-Ting Chen ,  Wei-Yu Chen ,  Chien-Wei Lee ,  Chung-Shi Liu

IPC: B23K31/02 ,  H01L21/00 ,  H05B3/02 ,  H01L21/677 ,  H01L21/683 ,  H01L23/00

CPC classification number: H05B3/02 ,  B23K3/087 ,  B23K2101/40 ,  H01L21/67721 ,  H01L21/6838 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/75744 ,  H01L2224/7598 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2924/3511 ,  H01L2924/37001 ,  Y10T29/41 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/014

Abstract: A method includes placing a first package component over a vacuum boat, wherein the vacuum boat comprises a hole, and wherein the first package component covers the hole. A second package component is placed over the first package component, wherein solder regions are disposed between the first and the second package components. The hole is vacuumed, wherein the first package component is pressed by a pressure against the vacuum boat, and wherein the pressure is generated by a vacuum in the hole. When the vacuum in the hole is maintained, the solder regions are reflowed to bond the second package component to the first package component.

Abstract translation: 一种方法包括将第一包装部件放置在真空舟皿上，其中真空舟皿包括孔，并且其中第一包装部件覆盖该孔。 第二包装部件放置在第一包装部件上，其中焊料区域设置在第一和第二包装部件之间。 该孔被抽真空，其中第一包装部件被压靠在真空舟皿上的压力，并且其中压力由孔中的真空产生。 当保持孔中的真空时，回流焊接区域以将第二包装部件结合到第一包装部件。

公开(公告)号：US08674496B2

公开(公告)日：2014-03-18

申请号：US13399437

申请日：2012-02-17

Applicant: Cheng-Chung Lin ,  Hsiu-Jen Lin ,  Cheng-Ting Chen ,  Chun-Cheng Lin ,  Ming-Da Cheng ,  Chung-Shi Liu

Inventor： Cheng-Chung Lin ,  Hsiu-Jen Lin ,  Cheng-Ting Chen ,  Chun-Cheng Lin ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L25/07

CPC classification number: H01L24/14 ,  H01L23/49816 ,  H01L23/5389 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00

Abstract: A fine pitch package-on-package (PoP), and a method of forming, are provided. The PoP may be formed by placing connections, e.g., solder balls, on a first substrate having a semiconductor die attached thereto. A first reflow process is performed to elongate the solder balls. Thereafter, a second substrate having another semiconductor die attached thereto is connected to the solder balls. A second reflow process is performed to form an hourglass connection.

Abstract translation: 提供了一种精细节距封装（PoP）和一种形成方法。 PoP可以通过将连接例如焊球放置在具有附接到其上的半导体管芯的第一基板上而形成。 执行第一回流处理以延长焊球。 此后，具有安装有另一个半导体管芯的第二基板连接到焊球。 执行第二回流处理以形成沙漏连接。