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    Bump Pad Metallurgy Employing An Electrolytic Cu / Electorlytic Ni / Electrolytic Cu Stack
    5.
    发明申请
    Bump Pad Metallurgy Employing An Electrolytic Cu / Electorlytic Ni / Electrolytic Cu Stack 失效
    使用电解Cu /电解Ni /电解铜堆栈的Bump Pad冶金

    公开(公告)号：US20090174045A1

    公开(公告)日：2009-07-09

    申请号：US11968663

    申请日：2008-01-03

    申请人： Charles L. Arvin ,  Hai P. Longworth ,  David J. Russell ,  Krystyna W. Semkow

    发明人： Charles L. Arvin ,  Hai P. Longworth ,  David J. Russell ,  Krystyna W. Semkow

    IPC分类号： H01L23/495 ,  H01L21/44

    CPC分类号： H01L23/49811 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/108 ,  H05K3/24 ,  H05K3/243 ,  H05K3/421 ,  H05K3/4644 ,  H05K2201/0341 ,  H05K2201/0769 ,  H05K2201/09481 ,  H05K2201/09563 ,  H01L2924/00

    摘要： An electroless Cu layer is formed on each side of a packaging substrate containing a core, at least one front metal interconnect layer, and at least one backside metal interconnect layer. A photoresist is applied on both electroless Cu layers and lithographically patterned. First electrolytic Cu portions are formed on exposed surfaces of the electroless Cu layers, followed by formation of electrolytic Ni portions and second electrolytic Cu portions. The electrolytic Ni portions provide enhanced resistance to electromigration, while the second electrolytic Cu portions provide an adhesion layer for a solder mask and serves as an oxidation protection layer. Some of the first electrolytic Cu may be masked by lithographic means to block formation of electrolytic Ni portions and second electrolytic Cu portions thereupon as needed. Optionally, the electrolytic Ni portions may be formed directly on electroless Cu layers.

    摘要翻译： 在包含芯，至少一个前金属互连层和至少一个背侧金属互连层的封装基板的每一侧上形成化学镀铜层。 在两个无电镀铜层上涂布光致抗蚀剂，并用光刻图案化。 第一电解Cu部分形成在无电解Cu层的暴露表面上，随后形成电解Ni部分和第二电解Cu部分。 电解Ni部分提供增强的电迁移阻力，而第二电解Cu部分提供用于焊接掩模的粘附层并且用作氧化保护层。 一些第一电解铜可以被光刻装置掩盖，以根据需要阻挡电解Ni部分和第二电解Cu部分的形成。 任选地，电解Ni部分可以直接形成在无电镀Cu层上。

    Photoimageable dielectric epoxy resin system film
    6.
    发明授权
    Photoimageable dielectric epoxy resin system film 失效
    可光成像介电环氧树脂体系膜

    公开(公告)号：US06835533B2

    公开(公告)日：2004-12-28

    申请号：US10781073

    申请日：2004-02-18

    申请人： Elizabeth Foster ,  Gary A. Johansson ,  Heike Marcello ,  David J. Russell

    发明人： Elizabeth Foster ,  Gary A. Johansson ,  Heike Marcello ,  David J. Russell

    IPC分类号： G03F7038

    CPC分类号： G03F7/0385 ,  G03F7/038 ,  H05K3/0023 ,  H05K3/4644 ,  H05K3/4676 ,  Y10T428/24851

    摘要： A method for fabricating circuitized substrates which reduces shorts, and does not require baking and resulting film. The method employs a photoimageable dielectric film, having a solvent content less than about 5%, and a glass transition temperature, when cured, which is greater than about 110° C. A photoimageable dielectric film is provided having from about 95% to about 100% solids, and comprising: from 0% to about 30% of the solids, of a particulate rheology modifier; from about 70% to about 100% of the solids of an epoxy resin system (liquid at 20° C.) comprising: from about 85% to about 99.9% epoxy resins; and from about 0.1 to 15 parts of the total resin weight, a cationic photoinitiator; from 0% to about 5% solvent; applying the photoimageable dielectric film to a circuitized substrate; and exposing the film to actinic radiation.

    摘要翻译： 一种制造电路化基板的方法，其减少短路，并且不需要烘烤和得到的膜。 该方法使用溶剂含量小于约5％的光致成像电介质膜，当固化时玻璃化转变温度大于约110℃。提供具有约95％至约100的光致成像电介质膜 ％固体，并且包含：0％至约30％的固体，颗粒状流变改性剂; 约70％至约100％的环氧树脂体系的固体（20℃的液体），包含：约85％至约99.9％的环氧树脂; 和约0.1至15份的总树脂重量，阳离子光引发剂; 0％至约5％的溶剂; 将光致成像电介质膜施加到电路化基板上; 并将膜暴露于光化辐射。

    Method of fabricating circuitized structures
    7.
    发明授权
    Method of fabricating circuitized structures 失效
    制造电路结构的方法

    公开(公告)号：US06706464B2

    公开(公告)日：2004-03-16

    申请号：US10345561

    申请日：2003-01-16

    申请人： Elizabeth Foster ,  Gary A. Johansson ,  Heike Marcello ,  David J. Russell

    发明人： Elizabeth Foster ,  Gary A. Johansson ,  Heike Marcello ,  David J. Russell

    IPC分类号： G03F740

    CPC分类号： G03F7/0385 ,  G03F7/038 ,  H05K3/0023 ,  H05K3/4644 ,  H05K3/4676 ,  Y10T428/24851

    摘要： A method for fabricating circuitized substrates which reduces shorts, and does not require baking and resulting film. The method employs a photoimageable dielectric film, having a solvent content less than about 5%, and a glass transition temperature, when cured, which is greater than about 110° C. A photoimageable dielectric film, is provided having from about 95% to about 100% solids, and comprising: from 0% to about 30% of the solids, of a particulate rheology modifier, from about 70% to about 100% of the solids of an epoxy resin system (liquid at 20° C. comprising: from about 85% to about 99.9% epoxy resins; and from about 0.1 to 15 parts of the total resin weight, a cationic photoinitiator; from 0 to about 5% solvent, applying the photoimageable dielectric film to a circuitized substrate; and exposing the film to actinic radiation.

    摘要翻译： 一种制造电路化基板的方法，其减少短路，并且不需要烘烤和得到的膜。 该方法采用溶剂含量小于约5％的光致成像电介质膜，当固化时玻璃化转变温度大于约110℃。提供了可见光电介质膜，其具有约95％至约 100％固体，并且包含：固体的0％至约30％的颗粒状流变改性剂，约70％至约100％的环氧树脂体系的固体（液体在20℃，包括：来自 约85％至约99.9％的环氧树脂;和约0.1至15份的总树脂重量，阳离子光引发剂; 0至约5％的溶剂，将可光成像的电介质膜施加到电路化基板;以及将膜暴露于 光化辐射。

    Method of forming a chip carrier by joining a laminate layer and stiffener
    8.
    发明授权
    Method of forming a chip carrier by joining a laminate layer and stiffener 失效
    通过接合层压层和加强件形成芯片载体的方法

    公开(公告)号：US06519843B2

    公开(公告)日：2003-02-18

    申请号：US09772418

    申请日：2001-01-30

    申请人： John M. Lauffer ,  Heike Marcello ,  David J. Russell

    发明人： John M. Lauffer ,  Heike Marcello ,  David J. Russell

    IPC分类号： H05K334

    CPC分类号： H05K3/0061 ,  H01L21/4803 ,  H01L23/36 ,  H01L2924/0002 ,  H05K1/183 ,  H05K3/0023 ,  H05K3/386 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/53178 ,  Y10T156/1798 ,  H01L2924/00

    摘要： A cavity-type chip module. The module is formed with an adhesive joining layer of photoimageable material interposed between a metal stiffener and a laminate top layer with a central aperture defined in the top layer. The photoimageable material is exposed to actinic radiation, except for an area corresponding to the aperture in the top layer. The unexposed area of photoimageable material is developed away to form a window in the joining layer. The top layer, joining layer, and stiffener are laminated together with the window and aperture aligned, and with a portion of the stiffener spanning the aperture to define a cavity in the resulting substrate. The removal of the unexposed photoimageable material, and the selective exposure of the joining layer to actinic radiation, keep the cavity free of photoimageable material and inhibit bleeding of the photoimageable material into the cavity from its inner edge. As a result, a semiconductor component can be flush mounted in the cavity with optimal thermal conductivity to the metal stiffener.

    摘要翻译： 腔型芯片模块。 该模块形成有介于金属加强件和层压顶层之间的可光成像材料的粘合剂接合层，中间孔限定在顶层中。 可光成像材料暴露于光化辐射，除了与顶层中的孔相对应的区域之外。 可光成像材料的未曝光区域被开发出来以在接合层中形成窗口。 将顶层，接合层和加强件层压在一起，窗口和孔对齐，并且加强件的一部分跨越孔以在所得到的基底中限定空腔。 未曝光的可光成像材料的去除以及将接合层选择性地暴露于光化辐射，保持空腔不含可光成像的材料并且抑制可光成像材料从其内边缘渗入空腔。 结果，半导体部件可以齐平地安装在空腔中，对金属加强件具有最佳的导热性。

    Process for manufacturing a multi-layer circuit board
    9.
    发明授权
    Process for manufacturing a multi-layer circuit board 失效
    制造多层电路板的工艺

    公开(公告)号：US06391210B2

    公开(公告)日：2002-05-21

    申请号：US09901848

    申请日：2001-07-09

    申请人： Bernd K. Appelt ,  John M. Lauffer ,  Voya R. Markovich ,  Irving Memis ,  David J. Russell

    发明人： Bernd K. Appelt ,  John M. Lauffer ,  Voya R. Markovich ,  Irving Memis ,  David J. Russell

    IPC分类号： H01B1300

    CPC分类号： H05K3/4652 ,  H05K3/0023 ,  H05K3/0035 ,  H05K2203/0508 ,  H05K2203/0554

    摘要： A circuit board having a structure including a permanent photoimageable dielectric material suitable for fabrication of vias both by laser ablation, plasma ablation, or mechanical drilling techniques and by photoimaging techniques. A process is also disclosed for the manufacture of a multi-level circuit on a substrate having a first-level circuitry pattern on at least one side. The process comprises applying a permanent photoimageable dielectric over the first-level circuitry pattern; exposing the permanent photoimageable dielectric to radiation; laminating a conductive metal layer to the dielectric; making holes in the conductive metal layer and dielectric by mechanical drilling or by laser or plasma ablation; and making a second-level circuitry pattern and filling the holes with a conductive material to electrically connect the first and second layers of circuitry. A further process is claimed for designing a multi-level circuit board product comprising making a prototype having the above structure in which the holes are manufactured by mechanical drilling or by laser or plasma ablation, evaluating the prototype, and then manufacturing a commercial circuit board having essentially the same structure and materials of construction as the prototype, but wherein the holes are manufactured by photoimaging techniques.

    摘要翻译： 一种电路板，其结构包括适用于通过激光烧蚀，等离子体消融或机械钻孔技术制造通孔的永久可光成像介电材料，以及通过光成像技术。 还公开了一种用于在至少一侧具有第一级电路图案的衬底上制造多电平电路的工艺。 该过程包括在第一级电路图案上施加永久可光成像电介质; 将永久可光成像电介质暴露于辐射; 将导电金属层层叠到电介质上; 通过机械钻孔或通过激光或等离子体消融在导电金属层和电介质中形成孔; 以及制作二级电路图案，并用导电材料填充所述孔，以电连接所述第一和第二层电路。 要求设计多级电路板产品的另一方法包括制造具有上述结构的原型，其中通过机械钻孔或通过激光或等离子体烧蚀制造孔，评估原型，然后制造商业电路板，其具有 基本上与原型相同的结构和结构材料，但是其中孔通过光成像技术制造。