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18 条记录 (耗时 0.019 秒)

    Temperature field controlled scheduling for processing systems
    3.
    发明授权
    Temperature field controlled scheduling for processing systems 有权
    温度场控制调度处理系统

    公开(公告)号：US07174194B2

    公开(公告)日：2007-02-06

    申请号：US09932361

    申请日：2001-08-17

    申请人： Gerard Chauvel ,  Dominique D'Inverno ,  Darvin R. Edwards

    发明人： Gerard Chauvel ,  Dominique D'Inverno ,  Darvin R. Edwards

    IPC分类号： H04B1/38 ,  G06F1/32 ,  G06F9/46

    CPC分类号： G06F9/4893 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/329 ,  G06F11/0724 ,  Y02D10/16 ,  Y02D10/24

    摘要： A multiprocessor system (10) includes a plurality of processing modules, such as MPUs (12), DSPs (14), and coprocessors/DMA channels (16). Power management software (38) in conjunction with profiles (36) for the various processing modules and the tasks to executed are used to build scenarios which meet predetermined power objectives, such as providing maximum operation within package thermal constraints or using minimum energy. Actual activities associated with the tasks are monitored during operation to ensure compatibility with the objectives. The allocation of tasks may be changed dynamically to accommodate changes in environmental conditions and changes in the task list. Temperatures may be computed at various points in the multiprocessor system by monitoring activity information associated with various subsystems. The activity measurements may be used to compute a current power dissipation distribution over the die. If necessary, the tasks in a scenario may be adjusted to reduce power dissipation. Further, activity counters may be selectively enabled for specific tasks in order to obtain more accurate profile information.

    摘要翻译： 多处理器系统（10）包括多个处理模块，例如MPU（12），DSP（14）和协处理器/ DMA通道（16）。 电力管理软件（38）结合用于各种处理模块的简档（36）和执行的任务被用于构建满足预定功率目标的场景，例如在封装热约束内提供最大操作或使用最小能量。 在操作过程中监视与任务相关的实际活动，以确保与目标的兼容性。 可以动态地改变任务的分配，以适应环境条件的变化和任务列表的变化。 可以通过监视与各种子系统相关联的活动信息来在多处理器系统中的各个点计算温度。 活动测量可用于计算模具上的当前功耗分布。 如果需要，可以调整场景中的任务以减少功耗。 此外，可以为特定任务选择性地启用活动计数器，以便获得更准确的简档信息。

    Multi-chip module testing
    6.
    发明授权
    Multi-chip module testing 失效
    多芯片模块测试

    公开(公告)号：US5321277A

    公开(公告)日：1994-06-14

    申请号：US112907

    申请日：1993-08-26

    申请人： Steve E. Sparks ,  Darvin R. Edwards ,  Katherine G. Heinen

    发明人： Steve E. Sparks ,  Darvin R. Edwards ,  Katherine G. Heinen

    IPC分类号： G01R31/28 ,  G01R31/3163 ,  G01R31/3185 ,  H01L23/48 ,  H01L23/46

    CPC分类号： G01R31/318541 ,  G01R31/2884 ,  G01R31/3163 ,  G01R31/318513 ,  H01L2924/0002

    摘要： A base for a multi-chip module that provides for built-in testability. Active test components are embedded in a module substrate. These test components primarily consist of boundary scan cells that comply with the IEEE 1149.1 test standard. The scan cells are connected to each other, and are connected to interconnection paths among chips and to individual chips, thereby partitioning the module into testable partitions. These partitions permit testing of chip interconnections, chip functionality, and module functionality. Scan cell connections may be mask programmable so that the same multi-chip module base can be used for many different multi-chip module configurations.

    摘要翻译： 用于提供内置可测试性的多芯片模块的基础。 主动测试组件嵌入在模块基板中。 这些测试组件主要由符合IEEE 1149.1测试标准的边界扫描单元组成。 扫描单元彼此连接，并且连接到芯片和单独芯片之间的互连路径，从而将模块划分成可测试分区。 这些分区允许测试芯片互连，芯片功能和模块功能。 扫描单元连接可以是可编程的，以便相同的多芯片模块可用于许多不同的多芯片模块配置。

    Wafer-scale assembly of chip-size packages
    8.
    发明授权
    Wafer-scale assembly of chip-size packages 有权
    芯片尺寸封装的晶圆尺寸组装

    公开(公告)号：US06730541B2

    公开(公告)日：2004-05-04

    申请号：US09186973

    申请日：1998-11-05

    申请人： Katherine G. Heinen ,  Darvin R. Edwards ,  Elizabeth G. Jacobs

    发明人： Katherine G. Heinen ,  Darvin R. Edwards ,  Elizabeth G. Jacobs

    IPC分类号： H01L2160

    CPC分类号： H01L21/67144 ,  H01L21/67138 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/00

    摘要： A wafer-scale assembly apparatus for integrated circuits and a method for forming the wafer-scale assembly are disclosed. A semiconductor wafer including a plurality of circuits is provided with a plurality of metal contact pads as electrical entry and exit ports. A first wafer-scale patterned polymer film carrying solder balls for each of the contact pads on the wafer is positioned opposite the wafer, and the wafer and the film are aligned. The film is brought into contact with the wafer. Radiant energy in the near infrared spectrum is applied to the backside of the wafer, heating the wafer uniformly and rapidly without moving the semiconductor wafer. Thermal energy is transferred through the wafer to the surface of the wafer and into the solder balls, which reflow onto the contact pads, while the thermal stretching of the polymer film is mechanically compensated. The uniformity of the height of the liquid solder balls is controlled either by mechanical stoppers or by the precision linear motion of motors. After cooling, the solder balls solidify and the first polymer film is removed. The process is repeated for assembling sequentially a wafer-scale patterned interposer overlying all of the solder balls and the wafer and contacting each solder ball with a soldered joint, and a second wafer-scale patterned film carrying solder balls contacting the interposer. In each process, the wafer is heated uniformly and rapidly and without moving it, the alignment is maintained during heating by mechanically compensating for the thermal stretching of the polymer film, and the uniformity of the height of the liquid solder balls is controlled by mechanical stoppers or position closed-loop linear actuators. The second film is removed after cooling. Other embodiments are also disclosed.

    摘要翻译： 公开了用于集成电路的晶片级组装装置和用于形成晶片级组件的方法。 包括多个电路的半导体晶片设置有多个金属接触垫作为电子入口和出口。 承载用于晶片上的每个接触焊盘的焊球的第一晶片级图案化聚合物膜与晶片相对定位，并且晶片和膜对准。 使膜与晶片接触。 将近红外光谱中的辐射能量施加到晶片的背面，均匀且快速地加热晶片而不移动半导体晶片。 热能通过晶片转移到晶片的表面并进入焊球，该焊球回流到接触焊盘上，同时机械补偿聚合物膜的热拉伸。 液体焊球的高度的均匀性由机械塞子或电动机的精密线性运动控制。 冷却后，焊球固化并除去第一聚合物膜。 重复该过程以顺序地组装覆盖所有焊球和晶片的晶片级图案化插层，并使每个焊球与焊接接头接触，以及承载接触插入件的焊球的第二晶片级图案膜。 在每个过程中，均匀且快速地加热晶片并且不移动晶片，在加热期间通过机械地补偿聚合物膜的热拉伸来维持对准，并且液体焊球的高度的均匀性由机械止动器 或定位闭环线性致动器。 冷却后除去第二层膜。 还公开了其他实施例。

    Method and apparatus to minimize power and ground bounce in a logic device
    10.
    发明授权
    Method and apparatus to minimize power and ground bounce in a logic device 有权
    最小化逻辑器件中的功率和接地反弹的方法和装置

    公开(公告)号：US07296168B2

    公开(公告)日：2007-11-13

    申请号：US11008341

    申请日：2004-12-09

    申请人： Darvin R. Edwards

    发明人： Darvin R. Edwards

    IPC分类号： G06F1/26

    CPC分类号： H03K19/00369

    摘要： A predictive power regulation apparatus and method that minimizes power and ground bounce in a logic device. The apparatus includes a predictor and a voltage or current smoothing device connected to the predictor. The voltage or current smoothing device outputs adjusted voltage or current to power and ground planes of the logic device. In one embodiment, the predictor includes an instruction scanner device and a look-up table connected to the instruction scanner device. The instruction scanner device determines the next instruction to be executed by the logic device. A voltage/current scheduling buffer connected to the look-up table contains voltage and current compensation and the time at which the voltage or current compensation should be requested from the voltage or current smoothing device. An alternative predictive power regulation apparatus is described that reduces power and ground bounce caused by the I/O buffer circuitry switching in the logic device.

    摘要翻译： 一种使逻辑器件中的功率和接地反弹最小化的预测功率调节装置和方法。 该装置包括连接到预测器的预测器和电压或电流平滑装置。 电压或电流平滑装置将调整的电压或电流输出到逻辑器件的电源和接地层。 在一个实施例中，预测器包括连接到指令扫描器装置的指令扫描器装置和查找表。 指令扫描器装置确定由逻辑装置执行的下一条指令。 连接到查找表的电压/电流调度缓冲器包含电压和电流补偿以及从电压或电流平滑装置请求电压或电流补偿的时间。 描述了一种替代的预测功率调节装置，其减少由逻辑器件中的I / O缓冲器电路切换引起的功率和接地反弹。