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    Compliant conductive nano-particle electrical interconnect
    1.
    发明授权
    Compliant conductive nano-particle electrical interconnect 有权
    符合导电纳米颗粒电气互连

    公开(公告)号：US08704377B2

    公开(公告)日：2014-04-22

    申请号：US13969953

    申请日：2013-08-19

    申请人： HSIO Technologies, LLC

    发明人： James Rathburn

    IPC分类号： H01L23/48

    CPC分类号： H01L23/48 ,  B82Y10/00 ,  H01R23/722 ,  H05K1/0231 ,  H05K1/113 ,  H05K1/141 ,  H05K3/32 ,  H05K3/3436 ,  H05K3/4038 ,  H05K3/4069 ,  H05K7/1069 ,  H05K7/1092 ,  H05K2201/049 ,  Y10T29/4913 ,  Y10T29/49147

    摘要： An electrical interconnect providing an interconnect between contacts on an IC device and contact pads on a printed circuit board (PCB). The electrical interconnect includes a resilient substrate with a plurality of through holes extending from a first surface to a second surface. A resilient material is located in the through holes. The resilient material includes an opening extending from the first surface to the second surface. A plurality of discrete, free-flowing conductive nano-particles are located in the openings of the resilient material. The conductive particles are substantially free of non-conductive materials. A plurality of first contact members are located in the through holes adjacent the first surface and a plurality of second contact members are located in the through holes adjacent the second surface. The first and second contact members are electrically coupled to the nano-particles.

    摘要翻译： 提供IC器件上的触点与印刷电路板（PCB）上的接触焊盘之间的互连的电互连。 电互连包括具有从第一表面延伸到第二表面的多个通孔的弹性基底。 弹性材料位于通孔中。 弹性材料包括从第一表面延伸到第二表面的开口。 多个离散的自由流动的导电纳米颗粒位于弹性材料的开口中。 导电颗粒基本上不含非导电材料。 多个第一接触构件位于邻近第一表面的通孔中，并且多个第二接触构件位于与第二表面相邻的通孔中。 第一和第二接触构件电耦合到纳米颗粒。

    COMPLIANT CORE PERIPHERAL LEAD SEMICONDUCTOR SOCKET
    3.
    发明申请
    COMPLIANT CORE PERIPHERAL LEAD SEMICONDUCTOR SOCKET 有权
    合格的核心外围导线半导体插座

    公开(公告)号：US20140043782A1

    公开(公告)日：2014-02-13

    申请号：US14058863

    申请日：2013-10-21

    申请人： HSIO TECHNOLOGIES, LLC

    发明人： James Rathburn

    IPC分类号： H01L23/522 ,  H05K3/40

    CPC分类号： H01L23/34 ,  G01R1/0416 ,  H01L23/522 ,  H01L2224/13 ,  H05K3/325 ,  H05K3/4007 ,  H05K2201/0133 ,  H05K2201/0187 ,  H05K2201/09036 ,  H05K2201/09481 ,  H05K2201/0949 ,  H05K2201/10378 ,  H05K2203/162 ,  Y10T29/49165

    摘要： An electrical interconnect between terminals on an IC device and contact pads on a printed circuit board (PCB). The electrical interconnect includes a substrate with a first surface having a plurality of openings arranged to correspond to the terminals on the IC device. A compliant material is located in the openings. A plurality of first conductive traces extend along the first surface of the substrate and onto the compliant material. The compliant material provides a biasing force that resists flexure of the first conductive traces into the openings. Vias extending through the substrate are electrically coupled the first conductive traces. A plurality of second conductive traces extend along the second surface of the substrate and are electrically coupled to a vias. The second conductive traces are configured to electrical couple with the contact pads on the PCB.

    摘要翻译： IC器件上的端子和印刷电路板（PCB）上的接触焊盘之间的电气互连。 电互连包括具有第一表面的基板，该第一表面具有多个开口，其布置成对应于IC器件上的端子。 柔性材料位于开口中。 多个第一导电迹线沿着衬底的第一表面延伸到柔性材料上。 柔性材料提供抵抗第一导电迹线弯曲到开口中的偏压力。 延伸穿过衬底的通孔电耦合第一导电迹线。 多个第二导电迹线沿着衬底的第二表面延伸并且电耦合到通孔。 第二导电迹线被配置为与PCB上的接触焊盘电耦合。

    Fusion bonded liquid crystal polymer circuit structure
    4.
    发明授权
    Fusion bonded liquid crystal polymer circuit structure 有权

    公开(公告)号：US10159154B2

    公开(公告)日：2018-12-18

    申请号：US14864215

    申请日：2015-09-24

    申请人： HSIO TECHNOLOGIES, LLC

    发明人： James Rathburn

    IPC分类号： H05K3/46 ,  C25D7/12 ,  H05K1/03 ,  C25D5/02 ,  C23C18/16 ,  H05K3/42 ,  B23K103/12 ,  B23K103/00 ,  C23C18/38

    摘要： A method of making a multilayered, fusion bonded circuit structure. A first circuitry layer is attached to a first major surface of a first LCP substrate. A plurality of first recesses are formed that extend from a second major surface of the first substrate to the first circuitry layer. The first recesses are then plated to form a plurality of first conductive pillars of solid metal that substantially fill the first recesses. A plurality of second recesses are formed in a second LCP substrate corresponding to a plurality of the first conductive pillars. The second recess are plated to form a plurality of second conductive structures that extend between first and second major surfaces of the second substrate. The second major surface of the first substrate is positioned adjacent to the second major surface of the second substrate. The first conductive pillars are aligned with the second conductive structures. The stack is then fusion bonded to mechanically couple the first conductive pillars to the second conductive structures.

    Performance enhanced semiconductor socket
    6.
    发明授权
    Performance enhanced semiconductor socket 有权

    公开(公告)号：US09689897B2

    公开(公告)日：2017-06-27

    申请号：US14565724

    申请日：2014-12-10

    申请人： HSIO TECHNOLOGIES, LLC

    发明人： James Rathburn

    IPC分类号： G01R1/04

    CPC分类号： G01R1/0466 ,  Y10T29/49222

    摘要： A test socket for IC devices includes a multi-layered socket housing with at least one center layer and first and second surface layers. The first and second surface layers have a thickness and dielectric constant less than that of the center layers. A plurality of contact members are located in center openings in the center layer with distal ends extending into openings in the first and second layers. The distal ends of the contact members having at least one dimension greater than the openings in the first and second surface layers to retain the contact members in the socket housing. The contact members include center portions with major diameters less than the diameters of the center openings, such that an air gap is maintained between the contact members and the center layer.

    High performance surface mount electrical interconnect
    7.
    发明授权
    High performance surface mount electrical interconnect 有权

    公开(公告)号：US09660368B2

    公开(公告)日：2017-05-23

    申请号：US14621663

    申请日：2015-02-13

    申请人： HSIO TECHNOLOGIES, LLC

    发明人： James Rathburn

    IPC分类号： H01R12/00 ,  H01R12/70 ,  H01R12/57

    CPC分类号： H01R12/7082 ,  H01R12/57 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49165

    摘要： An interconnect assembly including a substrate with a plurality of through holes extending from a first surface to a second surface. A plurality of discrete contact member are located in the plurality of through holes. The contact members include proximal ends that are accessible from the second surface, distal ends extending above the first surface, and intermediate portions engaged with an engagement region of the substrate located between the first surface and the recesses. Retention members are coupled with at least a portion of the proximal ends to retain the contact members in the through holes. The retention members can be made from a variety of materials with different levels of conductivity, ranging from highly conductive to non-conductive.