公开(公告)号：US20110233777A1

公开(公告)日：2011-09-29

申请号：US13154550

申请日：2011-06-07

Applicant: Salman Akram ,  Charles Watkins ,  Mark Hiatt ,  David Hembree ,  James Wark ,  Warren Farnworth ,  Mark Tuttle ,  Sidney Rigg ,  Steven Oliver ,  Kyle Kirby ,  Alan Wood ,  Lu Velicky

Inventor： Salman Akram ,  Charles Watkins ,  Mark Hiatt ,  David Hembree ,  James Wark ,  Warren Farnworth ,  Mark Tuttle ,  Sidney Rigg ,  Steven Oliver ,  Kyle Kirby ,  Alan Wood ,  Lu Velicky

IPC: H01L23/498 ,  H01L23/48

CPC classification number: H01L21/76877 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/45 ,  H01L27/14634 ,  H01L27/14636 ,  H01L2221/6834 ,  H01L2224/02166 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

Abstract translation: 公开了一种用于成像器，存储器和其他集成电路应用的透晶片互连，从而消除了对引线接合的需要，使得结合这种互连的器件可堆叠并且实现成像器件的晶片级封装。 此外，实现了更小且更可靠的管芯封装，并且由于信号路径长度的减小，电路寄生（例如，L和R）被减小。

公开(公告)号：US20070017093A1

公开(公告)日：2007-01-25

申请号：US11528137

申请日：2006-09-27

Applicant: James Wark ,  Salman Akram

Inventor： James Wark ,  Salman Akram

IPC: H01R43/00

CPC classification number: H01R12/57 ,  G01R1/0408 ,  G01R1/0466 ,  H01L2924/0002 ,  H01R43/205 ,  H05K1/119 ,  H05K3/325 ,  H05K3/326 ,  H05K3/4007 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/09045 ,  H05K2201/09472 ,  H05K2201/10689 ,  Y10T29/49117 ,  Y10T29/49123 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49174 ,  Y10T29/49179 ,  Y10T29/49222 ,  Y10T29/49453 ,  H01L2924/00

Abstract: A method of making an interposer having an array of contact structures for making temporary electrical contact with the leads of a chip package. The contact structures may make contact with the leads as close as desired to the body of the chip package. Moreover, the contact structures can be adapted for making contact with leads having a very fine pitch. In one embodiment, the contact structures include raised members formed over a body of the interposer. A conductive layer is formed over each of the raised members to provide a contact surface for engaging the leads of the chip package. In another embodiment, the raised members are replaced with depressions formed into the interposer. A conductive layer is formed on an inside surface of each depression to provide a contact surface for engaging the leads of the chip package. Any combination of raised members and depressions may be used.

Abstract translation: 一种制造具有用于与芯片封装的引线暂时电接触的接触结构阵列的插入件的方法。 接触结构可以使引线接近芯片封装体的所需位置。 此外，接触结构可以适于与具有非常细的间距的引线接触。 在一个实施例中，接触结构包括形成在插入件的主体上的凸起部件。 在每个凸起构件上形成导电层，以提供用于接合芯片封装引线的接触表面。 在另一个实施例中，凸起构件被形成在插入件中的凹陷所代替。 在每个凹陷的内表面上形成导电层，以提供用于接合芯片封装的引线的接触表面。 可以使用凸起构件和凹陷的任何组合。

公开(公告)号：US20060043512A1

公开(公告)日：2006-03-02

申请号：US10925406

申请日：2004-08-24

Applicant: Steven Oliver ,  James Wark ,  Kyle Kirby

Inventor： Steven Oliver ,  James Wark ,  Kyle Kirby

IPC: H01L31/0232

CPC classification number: H04N5/2254 ,  B33Y80/00 ,  G02B7/006 ,  G02B7/022 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/14685 ,  H01L31/02325 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15174 ,  H04N5/2253 ,  H01L2924/00014

Abstract: Microelectronic imager assemblies with optical devices having integral reference features and methods for assembling such microelectronic imagers is disclosed herein. In one embodiment, the imager assembly can include a workpiece with a substrate having a front side, a back side, and a plurality of imaging dies on and/or in the substrate. The imaging dies include image sensors, integrated circuitry operatively coupled to the image sensors, and external contacts electrically coupled to the integrated circuitry. The assembly also includes optics supports on the workpiece. The optics supports have openings aligned with corresponding image sensors and first interface features at reference locations relative to corresponding image sensors. The assembly further includes optical devices having optics elements and second interface features seated with corresponding first interface features to position the optics elements at a desired location relative to corresponding image sensors.

Abstract translation: 本文公开了具有整体参考特征的光学装置的微电子成像器组件和用于组装这种微电子成像器的方法。 在一个实施例中，成像器组件可以包括具有衬底的工件，其具有在衬底上和/或衬底中的前侧，后侧和多个成像管芯。 成像管芯包括图像传感器，可操作地耦合到图像传感器的集成电路以及电耦合到集成电路的外部触点。 组件还包括工件上的光学支架。 光学支架具有与对应的图像传感器对准的开口和相对于相应图像传感器的参考位置处的第一界面特征。 组件还包括具有光学元件的光学装置和与对应的第一界面特征相对的第二界面特征，以将光学元件相对于相应的图像传感器定位在期望的位置。

公开(公告)号：US20060003569A1

公开(公告)日：2006-01-05

申请号：US11210606

申请日：2005-08-23

Applicant: Warren Farnworth ,  Alan Wood ,  James Wark ,  David Hembree ,  Syed Ahmad ,  Michael Hess ,  John Jacobson

Inventor： Warren Farnworth ,  Alan Wood ,  James Wark ,  David Hembree ,  Syed Ahmad ,  Michael Hess ,  John Jacobson

IPC: H01L21/44

CPC classification number: H01L23/544 ,  B33Y30/00 ,  B33Y80/00 ,  H01L21/563 ,  H01L23/293 ,  H01L23/3157 ,  H01L24/81 ,  H01L24/83 ,  H01L2223/5448 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/11005 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/16 ,  H01L2224/293 ,  H01L2224/81011 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83851 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/05599

Abstract: Methods of manufacturing semiconductor devices using permanent or temporary polymer layers having apertures to expose contact pads and cover the active surfaces of the semiconductor devices.

公开(公告)号：US20050233482A1

公开(公告)日：2005-10-20

申请号：US11152433

申请日：2005-06-14

Applicant: Kyle Kirby ,  Warren Farnworth ,  James Wark ,  William Hiatt ,  David Hembree ,  Alan Wood

Inventor： Kyle Kirby ,  Warren Farnworth ,  James Wark ,  William Hiatt ,  David Hembree ,  Alan Wood

IPC: G01R1/073 ,  H01L21/66 ,  H01L23/48 ,  H01L23/498 ,  H01L23/58 ,  H01R13/24 ,  H05K3/32 ,  H05K3/40 ,  H05K7/06 ,  H05K7/10

CPC classification number: G01R1/0735 ,  G01R1/07314 ,  H01L23/13 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01R12/714 ,  H01R13/24 ,  H01R2201/20 ,  H05K3/326 ,  H05K7/1069 ,  H05K2201/0314 ,  H05K2201/09036 ,  H05K2201/10378 ,  Y10T29/49165 ,  Y10T29/49174 ,  Y10T29/49204 ,  Y10T29/49222 ,  H01L2224/05599

Abstract: A compliant contact pin contactor card method for making is provided. A compliant contact pin assembly includes a contact pin formed from a portion of a substrate with the contact pin compliantly held suspended within the substrate by a compliant coupling structure. The suspension within the substrate results in a compliant deflection orthogonal to the plane of the substrate. The contact pin assembly is formed by generally thinning the substrate around the contact pin location and then specifically thinning the substrate immediately around the contact pin location for forming a void. The contact pin is compliantly coupled, in one embodiment by compliant coupling material, and in another embodiment by compliantly flexible portions of the substrate.

Abstract translation: 提供一种兼容的接触针接触器卡制造方法。 柔性接触销组件包括由衬底的一部分形成的接触针，其中触发销通过柔性耦合结构顺应地保持悬挂在衬底内。 衬底内的悬浮液导致与衬底的平面垂直的柔顺偏转。 接触销组件通过使基板围绕接触销位置大体变薄而形成，然后特别地使基板在接触销位置周围特别地变薄以形成空隙。 在一个实施例中，接触销被顺从地联接，在一个实施例中通过柔性耦合材料，并且在另一个实施例中，通过柔性柔性部分的衬底。

公开(公告)号：US20050161796A1

公开(公告)日：2005-07-28

申请号：US11086144

申请日：2005-03-22

Applicant: James Wark

Inventor： James Wark

IPC: H01L21/00 ,  H01L21/44 ,  H01L21/48 ,  H01L21/60 ,  H01L21/98 ,  H01L23/52 ,  H01L25/065

CPC classification number: H01L24/85 ,  G11C5/04 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/85 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  Y10T29/49004 ,  Y10T29/49144 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a base, such as a printed circuit board, having a surface on which flip-chip pads and wire-bondable pads are provided. The flip-chip pads define an area on the surface of the base at least partially bounded by the wire-bondable pads. A first integrated circuit (IC) die is flip-chip bonded to the flip-chip pads, and a second IC die is back-side attached to the first IC die and then wire-bonded to the wire-bondable pads. As a result, the flip-chip mounted first IC die is stacked with the second IC die in a simple, novel manner.

公开(公告)号：US20070088451A1

公开(公告)日：2007-04-19

申请号：US11545067

申请日：2006-10-06

Applicant: Salman Akram ,  Warren Farnworth ,  Derek Gouchnour ,  David Hembree ,  Michael Hess ,  John Jacobson ,  James Wark ,  Alan Wood

Inventor： Salman Akram ,  Warren Farnworth ,  Derek Gouchnour ,  David Hembree ,  Michael Hess ,  John Jacobson ,  James Wark ,  Alan Wood

IPC: G06F19/00

CPC classification number: G03F7/7065 ,  G06F11/006 ,  H01L2223/5444

Abstract: An inventive method in an integrated circuit (IC) manufacturing process for using data regarding repair procedures conducted on ICs at probe to determine whether any further repairs will be conducted later in the manufacturing process includes storing the data in association with a fuse ID of each of the ICs. The ID codes of the ICs are automatically read, for example, at an opens/shorts test during the manufacturing process. The data stored in association with the ID codes of the ICs is then accessed, and additional repair procedures the ICs may undergo are selected in accordance with the accessed data. Thus, for example, the accessed data may indicate that an IC is unrepairable, so the IC can proceed directly to a scrap bin without having to be queried to determine whether it is repairable, as is necessary in traditional IC manufacturing processes.

Abstract translation: 在集成电路（IC）制造过程中的创造性方法，用于使用关于在探针上的IC进行的修复程序的数据，以确定是否在制造过程中稍后进行进一步的修理，包括将数据与每个的熔丝ID相关联地存储 IC。 IC的ID代码在制造过程中例如在打开/短路测试中自动读取。 然后访问与IC的ID代码相关联存储的数据，并且根据所访问的数据选择IC可能经历的附加修复过程。 因此，例如，访问的数据可以指示IC不可修复，因此IC可以直接进入废料仓，而不必被查询以确定其是否可修复，如在传统IC制造过程中所必需的。

公开(公告)号：US20070069372A1

公开(公告)日：2007-03-29

申请号：US11603581

申请日：2006-11-22

Applicant: Salman Akram ,  James Wark

Inventor： Salman Akram ,  James Wark

IPC: H01L23/34

CPC classification number: H01L24/85 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/42 ,  H01L23/4334 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/48465 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/75 ,  H01L2224/81801 ,  H01L2224/83951 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/8592 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00011 ,  H01L2224/78 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/85399

Abstract: An apparatus and a method for providing a heat sink on an upper surface of a semiconductor chip by placing a heat-dissipating material thereon which forms a portion of a glob top. The apparatus comprises a semiconductor chip attached to and in electrical communication with a substrate. A barrier glob top material is applied to the edges of the semiconductor chip on the surface (“opposing surface”) opposite the surface attached to the substrate to form a wall around a periphery of the opposing surface of the semiconductor chip wherein the barrier glob top material also extends to contact and adhere to the substrate. The wall around the periphery of the opposing surface of the semiconductor chip forms a recess. A heat-dissipating glob top material is disposed within the recess to contact the opposing surface of the semiconductor chip.

Abstract translation: 一种通过在其上放置形成球顶部的一部分的散热材料在半导体芯片的上表面上提供散热器的装置和方法。 该装置包括附接到衬底并与衬底电连通的半导体芯片。 将阻挡球顶部材料施加到与附接到基板的表面相对的表面（“相对表面”）上的半导体芯片的边缘，以形成围绕半导体芯片的相对表面的周边的壁，其中阻挡球顶部 材料也延伸到接触并粘附到基底上。 围绕半导体芯片的相对表面的周边的壁形成凹部。 散热球形材料设置在凹部内以接触半导体芯片的相对表面。

公开(公告)号：US20070063327A1

公开(公告)日：2007-03-22

申请号：US11601970

申请日：2006-11-20

Applicant: James Wark

Inventor： James Wark

IPC: H01L23/02

CPC classification number: H01L24/85 ,  G11C5/04 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/85 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  Y10T29/49004 ,  Y10T29/49144 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a base, such as a printed circuit board, having a surface on which flip-chip pads and wire-bondable pads are provided. The flip-chip pads define an area on the surface of the base at least partially bounded by the wire-bondable pads. A first integrated circuit (IC) die is flip-chip bonded to the flip-chip pads, and a second IC die is back-side attached to the first IC die and then wire-bonded to the wire-bondable pads. As a result, the flip-chip mounted first IC die is stacked with the second IC die in a simple, novel manner.

Abstract translation: 诸如多芯片模块（MCM），单列直插式存储器模块（SIMM）或双列直插存储器模块（DIMM）的创新的电子设备包括诸如印刷电路板的基座， 具有倒装芯片焊盘和可焊接焊盘的表面。 倒装芯片焊盘限定基部表面上至少部分地由可焊接焊盘限定的区域。 将第一集成电路（IC）晶片倒装芯片接合到倒装芯片焊盘，并且将第二IC裸片背面安装到第一IC裸片上，然后引线键合到可焊接焊盘。 结果，以简单，新颖的方式将倒装芯片安装的第一IC芯片与第二IC芯片堆叠。

公开(公告)号：US20070063229A1

公开(公告)日：2007-03-22

申请号：US11601969

申请日：2006-11-20

Applicant: James Wark

Inventor： James Wark

IPC: H01L27/148 ,  H01L29/76 ,  H01L29/768 ,  H01L29/94 ,  H01L31/00

CPC classification number: H01L24/85 ,  G11C5/04 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/85 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  Y10T29/49004 ,  Y10T29/49144 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a base, such as a printed circuit board, having a surface on which flip-chip pads and wire-bondable pads are provided. The flip-chip pads define an area on the surface of the base at least partially bounded by the wire-bondable pads. A first integrated circuit (IC) die is flip-chip bonded to the flip-chip pads, and a second IC die is back-side attached to the first IC die and then wire-bonded to the wire-bondable pads. As a result, the flip-chip mounted first IC die is stacked with the second IC die in a simple, novel manner.