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1.发明申请INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TRANSPARENT ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF 有权具有透明封装的集成电路包装系统及其制造方法公开(公告)号：US20120241927A1
公开(公告)日：2012-09-27
申请号：US13071760
申请日：2011-03-25
IPC分类号： H01L23/495 , H01L21/56
CPC分类号： H01L23/49816 , H01L21/561 , H01L23/147 , H01L23/3128 , H01L23/49827 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/97 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/12041 , H01L2924/12042 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2224/81 , H01L2924/00012 , H01L2924/00
摘要： A method of manufacture of an integrated circuit packaging system includes: forming a substrate having a redistribution line thereon; mounting an integrated circuit to the substrate; and molding a transparent encapsulation over the substrate covering the integrated circuit and the redistribution line and the integrated circuit seen through the transparent encapsulation.
摘要翻译： 一种集成电路封装系统的制造方法，包括：在其上形成具有再分布线的基板; 将集成电路安装到基板上; 以及在覆盖集成电路的衬底和通过透明封装看到的再分配线和集成电路上模制透明封装。
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2.发明授权Integrated circuit packaging system with transparent encapsulation and method of manufacture thereof 有权具有透明封装的集成电路封装系统及其制造方法公开(公告)号：US08399306B2
公开(公告)日：2013-03-19
申请号：US13071760
申请日：2011-03-25
IPC分类号： H01L21/00
CPC分类号： H01L23/49816 , H01L21/561 , H01L23/147 , H01L23/3128 , H01L23/49827 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/97 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/12041 , H01L2924/12042 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2224/81 , H01L2924/00012 , H01L2924/00
摘要： A method of manufacture of an integrated circuit packaging system includes: forming a substrate having a redistribution line thereon; mounting an integrated circuit to the substrate; and molding a transparent encapsulation over the substrate covering the integrated circuit and the redistribution line and the integrated circuit seen through the transparent encapsulation.
摘要翻译： 一种集成电路封装系统的制造方法，包括：在其上形成具有再分布线的基板; 将集成电路安装到基板上; 以及在覆盖集成电路的衬底和通过透明封装看到的再分配线和集成电路上模制透明封装。
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3.发明授权Semiconductor device and method of forming TSV interposer with semiconductor die and build-up interconnect structure on opposing surfaces of the interposer 有权半导体器件和在内插器的相对表面上形成具有半导体管芯和堆积互连结构的TSV插入器的方法公开(公告)号：US09224647B2
公开(公告)日：2015-12-29
申请号：US13184253
申请日：2011-07-15
IPC分类号： H01L23/48 , H01L21/56 , H01L21/768 , H01L21/48 , H01L23/14 , H01L25/065 , H01L25/10 , H01L25/00 , H01L23/31 , H01L23/498 , H01L23/00 , H01L25/18
CPC分类号： H01L21/76898 , H01L21/486 , H01L21/561 , H01L21/568 , H01L23/147 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/73 , H01L24/81 , H01L24/92 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L25/50 , H01L2224/0345 , H01L2224/03452 , H01L2224/03464 , H01L2224/0401 , H01L2224/05009 , H01L2224/0557 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/06181 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/32225 , H01L2224/48091 , H01L2224/73204 , H01L2224/73265 , H01L2224/81192 , H01L2224/81201 , H01L2224/81411 , H01L2224/81424 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/81815 , H01L2224/92125 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/1431 , H01L2924/1433 , H01L2924/14335 , H01L2924/1434 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/3511 , H01L2224/81 , H01L2924/00 , H01L2924/00012 , H01L2224/05552 , H01L2224/83
摘要： A semiconductor device has a substrate with first and second opposing surfaces. A plurality of conductive vias is formed partially through the first surface of the substrate. A first conductive layer is formed over the first surface of the substrate electrically connected to the conductive vias. A first semiconductor die is mounted over the first surface of the substrate. The first semiconductor die and substrate are mounted to a carrier. An encapsulant is deposited over the first semiconductor die, substrate, and carrier. A portion of the second surface of the substrate is removed to expose the conductive vias. An interconnect structure is formed over a surface of the substrate opposite the first semiconductor die. A second semiconductor die can be stacked over the first semiconductor die. A second semiconductor die can be mounted over the first surface of the substrate adjacent to the first semiconductor die.
摘要翻译： 半导体器件具有带有第一和第二相对表面的衬底。 多个导电通孔部分地形成在衬底的第一表面上。 在与导电通孔电连接的基板的第一表面上形成第一导电层。 第一半导体管芯安装在衬底的第一表面上。 第一半导体管芯和衬底安装到载体上。 密封剂沉积在第一半导体管芯，衬底和载体上。 去除衬底的第二表面的一部分以露出导电通孔。 在与第一半导体管芯相对的衬底的表面上形成互连结构。 第二半导体管芯可以堆叠在第一半导体管芯上。 第二半导体管芯可以安装在与第一半导体管芯相邻的衬底的第一表面上。
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4.发明申请Semiconductor Device and Method of Forming TSV Interposer With Semiconductor Die and Build-Up Interconnect Structure on Opposing Surfaces of the Interposer 有权半导体器件和形成具有半导体晶片的TSV插入件的方法和内插器的相对表面上的建立互连结构公开(公告)号：US20120074585A1
公开(公告)日：2012-03-29
申请号：US13184253
申请日：2011-07-15
CPC分类号： H01L21/76898 , H01L21/486 , H01L21/561 , H01L21/568 , H01L23/147 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/73 , H01L24/81 , H01L24/92 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L25/50 , H01L2224/0345 , H01L2224/03452 , H01L2224/03464 , H01L2224/0401 , H01L2224/05009 , H01L2224/0557 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/06181 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/32225 , H01L2224/48091 , H01L2224/73204 , H01L2224/73265 , H01L2224/81192 , H01L2224/81201 , H01L2224/81411 , H01L2224/81424 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/81815 , H01L2224/92125 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/1431 , H01L2924/1433 , H01L2924/14335 , H01L2924/1434 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/3511 , H01L2224/81 , H01L2924/00 , H01L2924/00012 , H01L2224/05552 , H01L2224/83
摘要： A semiconductor device has a substrate with first and second opposing surfaces. A plurality of conductive vias is formed partially through the first surface of the substrate. A first conductive layer is formed over the first surface of the substrate electrically connected to the conductive vias. A first semiconductor die is mounted over the first surface of the substrate. The first semiconductor die and substrate are mounted to a carrier. An encapsulant is deposited over the first semiconductor die, substrate, and carrier. A portion of the second surface of the substrate is removed to expose the conductive vias. An interconnect structure is formed over a surface of the substrate opposite the first semiconductor die. A second semiconductor die can be stacked over the first semiconductor die. A second semiconductor die can be mounted over the first surface of the substrate adjacent to the first semiconductor die.
摘要翻译： 半导体器件具有带有第一和第二相对表面的衬底。 多个导电通孔部分地形成在衬底的第一表面上。 在与导电通孔电连接的基板的第一表面上形成第一导电层。 第一半导体管芯安装在衬底的第一表面上。 第一半导体管芯和衬底安装到载体上。 密封剂沉积在第一半导体管芯，衬底和载体上。 去除衬底的第二表面的一部分以露出导电通孔。 在与第一半导体管芯相对的衬底的表面上形成互连结构。 第二半导体管芯可以堆叠在第一半导体管芯上。 第二半导体管芯可以安装在与第一半导体管芯相邻的衬底的第一表面上。
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5.发明申请INTEGRATED CIRCUIT SYSTEM WITH DEBONDING ADHESIVE AND METHOD OF MANUFACTURE THEREOF 有权具有绝缘胶的集成电路系统及其制造方法公开(公告)号：US20150311180A1
公开(公告)日：2015-10-29
申请号：US14791287
申请日：2015-07-03
IPC分类号： H01L23/00 , H01L21/78 , H01L23/528 , H01L23/48
CPC分类号： H01L24/94 , H01L21/6835 , H01L21/6836 , H01L21/78 , H01L23/481 , H01L23/528 , H01L24/03 , H01L24/11 , H01L24/26 , H01L24/27 , H01L24/29 , H01L24/83 , H01L2221/68318 , H01L2221/68327 , H01L2221/68381 , H01L2224/03002 , H01L2224/0401 , H01L2224/0557 , H01L2224/06181 , H01L2224/13025 , H01L2224/13082 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/27848 , H01L2224/29187 , H01L2224/8389 , H01L2224/94 , H01L2924/05432 , H01L2924/05442 , H01L2924/10253 , H01L2924/14 , H01L2924/20106 , H01L2224/11 , H01L2224/03 , H01L2924/014
摘要： A system and method of manufacture of an integrated circuit system includes: a die having a via, the die having a top side and a bottom side; a top interconnect mounted to the via at the top side; an interconnect pillar mounted to the via at the bottom side; a device interconnect mounted to the interconnect pillar; and a base adhesive covering the interconnect pillar and the device interconnect.
摘要翻译： 一种集成电路系统的制造方法，其特征在于，包括具有通孔的模具，所述模具具有顶侧和底面; 安装在顶侧的通孔的顶部互连; 安装在底面的通孔的互连柱; 安装到所述互连柱的器件互连; 以及覆盖互连柱和器件互连的基底粘合剂。
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6.发明授权Integrated circuit package system with post-passivation interconnection and integration 有权具有后钝化互连和集成的集成电路封装系统公开(公告)号：US08951904B2
公开(公告)日：2015-02-10
申请号：US13456145
申请日：2012-04-25
IPC分类号： H01L23/488 , H01L23/525 , H01L23/00 , H01L23/522 , H01L23/532
CPC分类号： H01L23/525 , H01L23/5227 , H01L23/53223 , H01L23/53238 , H01L24/11 , H01L2224/05001 , H01L2224/05022 , H01L2224/05026 , H01L2224/05027 , H01L2224/0508 , H01L2224/05111 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05181 , H01L2224/05571 , H01L2224/05647 , H01L2924/14 , H01L2924/00 , H01L2924/00014
摘要： An integrated circuit package system including: providing an integrated circuit die, forming a first layer over the integrated circuit die, forming a bridge on and in the first layer, forming a second layer on the first layer, and forming bump pads on and in the second layer, the bump pads connected to ends of the bridge.
摘要翻译： 一种集成电路封装系统，包括：提供集成电路管芯，在所述集成电路管芯上形成第一层，在所述第一层上并在所述第一层中形成桥，在所述第一层上形成第二层，以及在所述第一层上形成凸块 第二层，凸块连接到桥的端部。
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7.发明申请Semiconductor Method of Device of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units 审中-公开具有PWB垂直互连单元的扇出PoP设备的半导体方法公开(公告)号：US20130249101A1
公开(公告)日：2013-09-26
申请号：US13477982
申请日：2012-05-22
申请人： Yaojian Lin , Pandi Chelvam Marimuthu , Kang Chen , Yu Gu
发明人： Yaojian Lin , Pandi Chelvam Marimuthu , Kang Chen , Yu Gu
CPC分类号： H01L23/3121 , H01L21/486 , H01L21/561 , H01L21/563 , H01L21/565 , H01L21/568 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/96 , H01L24/97 , H01L25/105 , H01L2224/12105 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/1023 , H01L2225/1035 , H01L2225/1058 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2924/3511 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device has a carrier with a die attach area. A semiconductor die is mounted to the die attach area with a back surface opposite the carrier. A modular interconnect unit is mounted over the carrier and around or in a peripheral region around the semiconductor die such that the modular interconnect unit is offset from the back surface of the semiconductor die. An encapsulant is deposited over the carrier, semiconductor die, and modular interconnect unit. A first portion of the encapsulant is removed to expose the semiconductor die and a second portion is removed to expose the modular interconnect unit. The carrier is removed. An interconnect structure is formed over the semiconductor die and modular interconnect unit. The modular interconnect unit includes a vertical interconnect structures or bumps through the semiconductor device. The modular interconnect unit forms part of an interlocking pattern around the semiconductor die.
摘要翻译： 半导体器件具有带有裸片附着区域的载体。 半导体管芯安装到具有与载体相对的后表面的管芯附着区域。 模块化互连单元安装在载体上并且围绕半导体管芯周围或周围区域安装，使得模块化互连单元偏离半导体管芯的后表面。 密封剂沉积在载体，半导体管芯和模块化互连单元上。 去除密封剂的第一部分以暴露半导体管芯，并且移除第二部分以露出模块化互连单元。 载体被移除。 在半导体管芯和模块化互连单元上形成互连结构。 模块化互连单元包括通过半导体器件的垂直互连结构或凸块。 模块化互连单元形成围绕半导体管芯的互锁图案的一部分。
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8.发明申请公开(公告)号：US20120205813A1
公开(公告)日：2012-08-16
申请号：US13456145
申请日：2012-04-25
IPC分类号： H01L23/488 , H01L21/768
CPC分类号： H01L23/525 , H01L23/5227 , H01L23/53223 , H01L23/53238 , H01L24/11 , H01L2224/05001 , H01L2224/05022 , H01L2224/05026 , H01L2224/05027 , H01L2224/0508 , H01L2224/05111 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05181 , H01L2224/05571 , H01L2224/05647 , H01L2924/14 , H01L2924/00 , H01L2924/00014
摘要： An integrated circuit package system including: providing an integrated circuit die, forming a first layer over the integrated circuit die, forming a bridge on and in the first layer, forming a second layer on the first layer, and forming bump pads on and in the second layer, the bump pads connected to ends of the bridge.
摘要翻译： 一种集成电路封装系统，包括：提供集成电路管芯，在所述集成电路管芯上形成第一层，在所述第一层上并在所述第一层中形成桥，在所述第一层上形成第二层，以及在所述第一层上形成凸块 第二层，凸块连接到桥的端部。
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9.发明授权Integrated circuit package system with post-passivation interconnection and integration 有权具有后钝化互连和集成的集成电路封装系统公开(公告)号：US08188590B2
公开(公告)日：2012-05-29
申请号：US11843649
申请日：2007-08-23
IPC分类号： H01L23/50
CPC分类号： H01L23/525 , H01L23/5227 , H01L23/53223 , H01L23/53238 , H01L24/11 , H01L2224/05001 , H01L2224/05022 , H01L2224/05026 , H01L2224/05027 , H01L2224/0508 , H01L2224/05111 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05181 , H01L2224/05571 , H01L2224/05647 , H01L2924/14 , H01L2924/00 , H01L2924/00014
摘要： An integrated circuit package system including: providing an integrated circuit die, forming a first layer over the integrated circuit die, forming a bridge on and in the first layer, forming a second layer on the first layer, and forming bump pads on and in the second layer, the bump pads connected to ends of the bridge.
摘要翻译： 一种集成电路封装系统，包括：提供集成电路管芯，在所述集成电路管芯上形成第一层，在所述第一层上并在所述第一层中形成桥，在所述第一层上形成第二层，以及在所述第一层上形成凸块 第二层，凸块连接到桥的端部。
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公开(公告)号：US20110101509A1
公开(公告)日：2011-05-05
申请号：US13004111
申请日：2011-01-11
IPC分类号： H01L23/552 , H01L23/48
CPC分类号： H01L23/147 , H01L21/563 , H01L23/49822 , H01L23/552 , H01L2224/05571 , H01L2224/05573 , H01L2224/16 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/15311 , H01L2924/16152 , H01L2924/19107 , H01L2924/3025 , H01L2224/05599
摘要： A semiconductor device has a wafer for supporting the device and a conductive layer formed over a top surface of the wafer. A carrier wafer is permanently bonded over the conductive layer. Within the wafer and the carrier wafer, an interconnect structure is formed. The interconnect structure includes a first via formed in the wafer that exposes the conductive layer, a second via formed in the carrier wafer that exposes the conductive layer, a first metal layer deposited over the first via, the first metal layer in electrical contact with the conductive layer, and a second metal layer deposited over the second via, the second metal layer in electrical contact with the conductive layer. First and second insulation layers are deposited over the first and second metal layers respectively. The first or second insulation layer has an etched portion to expose a portion of the first or second metal layer.
摘要翻译： 半导体器件具有用于支撑器件的晶片和形成在晶片顶表面上的导电层。 载体晶片永久地接合在导电层上。 在晶片和载体晶片内形成互连结构。 所述互连结构包括形成在所述晶片中的第一通孔，所述第一通孔暴露所述导电层，形成在所述载体晶片中的暴露所述导电层的第二通孔，沉积在所述第一通孔上的第一金属层，所述第一金属层与所述导电层电接触; 导电层和沉积在第二通孔上的第二金属层，第二金属层与导电层电接触。 第一和第二绝缘层分别沉积在第一和第二金属层上。 第一或第二绝缘层具有蚀刻部分以暴露第一或第二金属层的一部分。
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