公开(公告)号：US07060624B2

公开(公告)日：2006-06-13

申请号：US10639989

申请日：2003-08-13

申请人： Panayotis Andricacos ,  Emanuel Israel Cooper ,  Timothy Joseph Dalton ,  Hariklia Deligianni ,  Daniel Guidotti ,  Keith Thomas Kwietniak ,  Michelle Leigh Steen ,  Cornelia Kang-I Tsang

发明人： Panayotis Andricacos ,  Emanuel Israel Cooper ,  Timothy Joseph Dalton ,  Hariklia Deligianni ,  Daniel Guidotti ,  Keith Thomas Kwietniak ,  Michelle Leigh Steen ,  Cornelia Kang-I Tsang

IPC分类号： H01L21/311

CPC分类号： H01L21/2885 ,  H01L21/30655 ,  H01L21/76898

摘要： Flared and non-flared metallized deep vias having aspect ratios of about 2 or greater are provided. Blind vias have been fabricated in silicon substrates up to a depth of about 300 microns, and flared through vias have been fabricated up to about 750 microns, the approximate thickness of a silicon substrate wafer, enabling the formation of electrical connections at either or both ends of a via.In spite of the depth and high aspect ratios attainable, the etched vias are completely filled with plated copper conductor, completing the formation of deep vias and allowing fuller use of both sides of the substrate.

摘要翻译： 提供具有约2或更大的纵横比的扩张和未扩口的金属化深通孔。 盲孔已经在硅衬底中制造达到约300微米的深度，并且通过通孔已经被制造高达约750微米，硅衬底晶片的大致厚度，使得能够在两端或两端形成电连接 的通道。 尽管可以获得深度和高纵横比，但是蚀刻的通孔完全被电镀铜导体填充，从而形成深通孔并允许更充分地使用基板的两侧。

公开(公告)号：US20050037608A1

公开(公告)日：2005-02-17

申请号：US10639989

申请日：2003-08-13

申请人： Panayotis Andricacos ,  Emanuel Cooper ,  Timothy Dalton ,  Hariklia Deligianni ,  Daniel Guidotti ,  Keith Kwietniak ,  Michelle Steen ,  Cornelia Tsang

发明人： Panayotis Andricacos ,  Emanuel Cooper ,  Timothy Dalton ,  Hariklia Deligianni ,  Daniel Guidotti ,  Keith Kwietniak ,  Michelle Steen ,  Cornelia Tsang

IPC分类号： H01L21/288 ,  H01L21/3065 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/2885 ,  H01L21/30655 ,  H01L21/76898

摘要： Flared and non-flared metallized deep vias having aspect ratios of about 2 or greater are provided. Blind vias have been fabricated in silicon substrates up to a depth of about 300 microns, and flared through vias have been fabricated up to about 750 microns, the approximate thickness of a silicon substrate wafer, enabling the formation of electrical connections at either or both ends of a via. In spite of the depth and high aspect ratios attainable, the etched vias are completely filled with plated copper conductor, completing the formation of deep vias and allowing fuller use of both sides of the substrate.

摘要翻译： 提供具有约2或更大的纵横比的扩张和未扩口的金属化深通孔。 盲孔已经在硅衬底中制造达到约300微米的深度，并且通过通孔已经被制造高达约750微米，硅衬底晶片的大致厚度，使得能够在两端或两端形成电连接 的通道。 尽管可以获得深度和高纵横比，但是蚀刻的通孔完全被电镀铜导体填充，从而形成深通孔并允许更充分地使用基板的两侧。

公开(公告)号：US20060076685A1

公开(公告)日：2006-04-13

申请号：US11265302

申请日：2005-11-03

申请人： Panayotis Andricacos ,  Shyng-Tsong Chen ,  John Cotte ,  Hariklia Deligianni ,  Mahadevaiyer Krishnan ,  Wei-Tsu Tseng ,  Philippe Vereecken

发明人： Panayotis Andricacos ,  Shyng-Tsong Chen ,  John Cotte ,  Hariklia Deligianni ,  Mahadevaiyer Krishnan ,  Wei-Tsu Tseng ,  Philippe Vereecken

IPC分类号： H01L23/48

CPC分类号： H01L21/76846 ,  H01L21/2885 ,  H01L21/6708 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76874 ,  H01L21/76883

摘要： Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided.

公开(公告)号：US06974531B2

公开(公告)日：2005-12-13

申请号：US10269956

申请日：2002-10-15

申请人： Panayotis Andricacos ,  Hariklia Deligianni ,  Wilma Jean Horkans ,  Keith T. Kwietniak ,  Michael Lane ,  Sandra G. Malhotra ,  Fenton Read McFeely ,  Conal Murray ,  Kenneth P. Rodbell ,  Philippe M. Vereecken

发明人： Panayotis Andricacos ,  Hariklia Deligianni ,  Wilma Jean Horkans ,  Keith T. Kwietniak ,  Michael Lane ,  Sandra G. Malhotra ,  Fenton Read McFeely ,  Conal Murray ,  Kenneth P. Rodbell ,  Philippe M. Vereecken

IPC分类号： C25D5/18 ,  C25D7/12 ,  B32B15/00

CPC分类号： C25D5/18 ,  C25D7/12 ,  Y10S428/926 ,  Y10T428/12493 ,  Y10T428/12528 ,  Y10T428/12771 ,  Y10T428/12778 ,  Y10T428/12903

摘要： A conductive material is electroplated onto a platable resistive metal barrier layer(s) employing a plating bath optionally comprising a super filling additive and a suppressor, and by changing the current or voltage as a function of the area of plated metal. A structure is also provided that comprises a substrate, a platable metal barrier layer(s) located on the substrate and a relatively continuous uniform electroplated layer of a conductive material located on the platable resistive metal barrier layer.

公开(公告)号：US20050167780A1

公开(公告)日：2005-08-04

申请号：US10768773

申请日：2004-01-29

申请人： Daniel Edelstein ,  Panayotis Andricacos ,  John Cotte ,  Hariklia Deligianni ,  John Magerlein ,  Kevin Petrarca ,  Kenneth Stein ,  Richard Volant

发明人： Daniel Edelstein ,  Panayotis Andricacos ,  John Cotte ,  Hariklia Deligianni ,  John Magerlein ,  Kevin Petrarca ,  Kenneth Stein ,  Richard Volant

IPC分类号： H01F41/04 ,  H01F17/00 ,  H01L21/02 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L27/08 ,  H01L23/48 ,  H01L21/8222

CPC分类号： H01L24/12 ,  H01L23/5227 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L27/08 ,  H01L28/10 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05014 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05084 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

摘要： An inductor and a method of forming and the inductor, the method including: (a) providing a semiconductor substrate; (b) forming a dielectric layer on a top surface of the substrate; (c) forming a lower trench in the dielectric layer; (d) forming a resist layer on a top surface of the dielectric layer; (e) forming an upper trench in the resist layer, the upper trench aligned to the lower trench, a bottom of the upper trench open to the lower trench; and (f) completely filling the lower trench at least partially filling the upper trench with a conductor in order to form the inductor. The inductor including a top surface, a bottom surface and sidewalls, a lower portion of said inductor extending a fixed distance into a dielectric layer formed on a semiconductor substrate and an upper portion extending above said dielectric layer; and means to electrically contact said inductor.

摘要翻译： 一种电感器及其形成方法和电感器，所述方法包括：（a）提供半导体衬底; （b）在所述基板的顶表面上形成电介质层; （c）在介电层中形成下沟槽; （d）在介电层的顶表面上形成抗蚀剂层; （e）在所述抗蚀剂层中形成上沟槽，所述上沟槽对准所述下沟槽，所述上沟槽的底部通向所述下沟槽; 和（f）用导体完全填充下沟槽至少部分地填充上沟槽，以形成电感器。 所述电感器包括顶表面，底表面和侧壁，所述电感器的下部将固定距离延伸到形成在半导体衬底上的电介质层和在所述电介质层上方延伸的上部; 以及用于电接触所述电感器的装置。

公开(公告)号：US20050006242A1

公开(公告)日：2005-01-13

申请号：US10615794

申请日：2003-07-10

申请人： Panayotis Andricacos ,  Dean Chung ,  Hariklia Deligianni ,  James Fluegel ,  Keith Kwietniak ,  Peter Locke ,  Darryl Restaino ,  Soon-Cheon Seo ,  Philippe Vereecken ,  Erick Walton

发明人： Panayotis Andricacos ,  Dean Chung ,  Hariklia Deligianni ,  James Fluegel ,  Keith Kwietniak ,  Peter Locke ,  Darryl Restaino ,  Soon-Cheon Seo ,  Philippe Vereecken ,  Erick Walton

IPC分类号： C23C18/16 ,  C25D21/12 ,  C25D21/18

CPC分类号： C23C18/1617 ,  C23C18/1683 ,  C25D21/12 ,  C25D21/18

摘要： An improved method of stabilizing wet chemical baths is disclosed. Typically such baths are used in processes for treating workpieces, for example, plating processes for plating metal onto substrates. In particular, the present invention relates to copper plating baths. More particularly, the present invention relates to the stability of copper plating baths. More particularly, the present invention relates to prevention of void formation by monitoring the accumulation of deleterious by-products in copper plating baths.

摘要翻译： 公开了一种稳定湿化学浴的改进方法。 通常，这种浴用于处理工件的工艺中，例如用于将金属电镀到基底上的电镀工艺。 特别地，本发明涉及镀铜浴。 更具体地说，本发明涉及镀铜浴的稳定性。 更具体地，本发明涉及通过监测铜电镀浴中有害副产物的积累来防止空隙形成。

公开(公告)号：US07581314B2

公开(公告)日：2009-09-01

申请号：US11358823

申请日：2006-02-21

申请人： Hariklia Deligianni ,  Panayotis Andricacos ,  L. Paivikki Buchwalter ,  John M. Cotte ,  Christopher Jahnes ,  Mahadevaiyer Krishnan ,  John H. Magerlein ,  Kenneth Stein ,  Richard P. Volant ,  James A. Tornello ,  Jennifer Lund

发明人： Hariklia Deligianni ,  Panayotis Andricacos ,  L. Paivikki Buchwalter ,  John M. Cotte ,  Christopher Jahnes ,  Mahadevaiyer Krishnan ,  John H. Magerlein ,  Kenneth Stein ,  Richard P. Volant ,  James A. Tornello ,  Jennifer Lund

IPC分类号： H01K3/10

CPC分类号： H01H59/0009 ,  H01H2001/0052 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49204

摘要： A semiconductor micro-electromechanical system (MEMS) switch provided with noble metal contacts that act as an oxygen barrier to copper electrodes is described. The MEMS switch is fully integrated into a CMOS semiconductor fabrication line. The integration techniques, materials and processes are fully compatible with copper chip metallization processes and are typically, a low cost and a low temperature process (below 400° C.). The MEMS switch includes: a movable beam within a cavity, the movable beam being anchored to a wall of the cavity at one or both ends of the beam; a first electrode embedded in the movable beam; and a second electrode embedded in an wall of the cavity and facing the first electrode, wherein the first and second electrodes are respectively capped by the noble metal contact.

摘要翻译： 描述了提供有作为铜电极的氧阻隔的贵金属触点的半导体微机电系统（MEMS）开关。 MEMS开关完全集成到CMOS半导体制造线中。 集成技术，材料和工艺完全兼容铜芯片金属化工艺，通常是低成本和低温工艺（低于400℃）。 MEMS开关包括：在空腔内的可移动光束，可移动光束在光束的一端或两端锚定到空腔的壁; 嵌入可移动光束中的第一电极; 以及第二电极，其嵌入在所述空腔的壁中并且面向所述第一电极，其中所述第一和第二电极分别被所述贵金属接触物覆盖。

公开(公告)号：US20060105534A1

公开(公告)日：2006-05-18

申请号：US11320375

申请日：2005-12-28

申请人： Daniel Edelstein ,  Panayotis Andricacos ,  John Cotte ,  Hariklia Deligianni ,  John Magerlein ,  Kevin Petrarca ,  Kenneth Stein ,  Richard Volant

发明人： Daniel Edelstein ,  Panayotis Andricacos ,  John Cotte ,  Hariklia Deligianni ,  John Magerlein ,  Kevin Petrarca ,  Kenneth Stein ,  Richard Volant

IPC分类号： H01L21/8222

CPC分类号： H01L24/12 ,  H01L23/5227 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L27/08 ,  H01L28/10 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05014 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05084 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

摘要： An inductor and a method of forming and the inductor, the method including: (a) forming a dielectric layer on a top surface of a substrate; (b) forming a lower trench in the dielectric layer; (c) forming a resist layer on a top surface of the dielectric layer; (d) forming an upper trench in the resist layer, the upper trench aligned to the lower trench, a bottom of the upper trench open to the lower trench; and (e) completely filling the lower trench at least partially filling the upper trench with a conductor in order to form the inductor. The inductor including a top surface, a bottom surface and sidewalls, a lower portion of said inductor extending a fixed distance into a dielectric layer formed on a semiconductor substrate and an upper portion extending above said dielectric layer; and means to electrically contact said inductor.

摘要翻译： 一种电感器及其形成方法和电感器，所述方法包括：（a）在基板的顶表面上形成电介质层; （b）在介电层中形成下沟槽; （c）在介电层的顶表面上形成抗蚀剂层; （d）在抗蚀剂层中形成上沟槽，上沟槽与下沟槽对准，上沟槽的底部通向下沟槽; 和（e）用导体完全填充下沟槽至少部分地填充上沟槽，以形成电感器。 所述电感器包括顶表面，底表面和侧壁，所述电感器的下部将固定距离延伸到形成在半导体衬底上的电介质层和在所述电介质层上方延伸的上部; 以及用于电接触所述电感器的装置。

公开(公告)号：US20060081885A1

公开(公告)日：2006-04-20

申请号：US11228269

申请日：2005-10-26

申请人： Katherine Saenger ,  Cyril Cabral ,  Hariklia Deligianni ,  Panayotis Andricacos ,  Caliopi Andricacos ,  Philippe Vereecken ,  Emanuel Cooper

发明人： Katherine Saenger ,  Cyril Cabral ,  Hariklia Deligianni ,  Panayotis Andricacos ,  Caliopi Andricacos ,  Philippe Vereecken ,  Emanuel Cooper

IPC分类号： H01L29/76 ,  H01L29/745

CPC分类号： H01L21/28088 ,  H01L29/4966 ,  H01L29/66621 ,  H01L29/7834

摘要： Disclosed is a method for making a metal gate for a FET, wherein the metal gate comprises at least some material deposited by electroplating as well as an FET device comprising a metal gate that is at least partially plated. Further disclosed is a method for making a metal gate for a FET wherein the metal gate comprises at least some plated material and the method comprises the steps of: selecting a substrate having a top surface and a recessed region; conformally depositing a thin conductive seed layer on the substrate; and electroplating a filler gate metal on the seed layer to fill and overfill the recessed region.

摘要翻译： 公开了一种用于制造用于FET的金属栅极的方法，其中金属栅极包括通过电镀沉积的至少一些材料以及包括至少部分镀覆的金属栅极的FET器件。 还公开了一种用于制造用于FET的金属栅极的方法，其中金属栅极包括至少一些镀层材料，并且该方法包括以下步骤：选择具有顶表面和凹陷区域的衬底; 在衬底上共形沉积导电种子层; 并在种子层上电镀填充栅极金属以填充和覆盖凹陷区域。

公开(公告)号：US20050241946A1

公开(公告)日：2005-11-03

申请号：US11016924

申请日：2004-12-21

申请人： Mizuki Nagai ,  Hiroyuki Kanda ,  Keiichi Kurashina ,  Satoru Yamamoto ,  Ryoichi Kimizuka ,  Hariklia Deligianni ,  Brett Baker ,  Keith Kwietniak ,  Panayotis Andricacos ,  Philippe Vereecken

发明人： Mizuki Nagai ,  Hiroyuki Kanda ,  Keiichi Kurashina ,  Satoru Yamamoto ,  Ryoichi Kimizuka ,  Hariklia Deligianni ,  Brett Baker ,  Keith Kwietniak ,  Panayotis Andricacos ,  Philippe Vereecken

IPC分类号： C25D3/38 ,  C25D5/00 ,  C25D5/02 ,  C25D5/08 ,  C25D5/18 ,  C25D7/12 ,  C25D17/00 ,  H01L21/288 ,  H01L21/768

CPC分类号： C25D3/38 ,  C25D5/02 ,  C25D5/18 ,  C25D7/123 ,  C25D17/001 ,  C25D17/007 ,  C25D17/008 ,  H01L21/2885 ,  H01L21/76877

摘要： A plating method is capable of mechanically and electrochemically preferentially depositing a plated film in fine interconnect recesses such as trenches and via holes, and depositing the plated film to a flatter surface. The plating method including: disposing a substrate having fine interconnect recesses such that a conductive layer faces an anode; disposing a porous member between the substrate and the anode; filling a plating solution between the substrate and the anode; and repeating a process of holding the conductive layer and the porous member in contact with each other and moving the conductive layer and the porous member relatively to each other, a process of passing an electric current between the conductive layer and the anode while keeping the conductive layer still with respect to the porous member, and a process of stopping the supply of the electric current between the conductive layer and the anode.

摘要翻译： 电镀方法能够机械地和电化学地优先在诸如沟槽和通孔的精细互连凹槽中沉积镀膜，并将镀膜沉积到更平坦的表面上。 电镀方法包括：设置具有导电层面向阳极的细微互连凹槽的衬底; 在基板和阳极之间设置多孔构件; 在基板和阳极之间填充电镀液; 并且重复保持导电层和多孔构件彼此接触并相对于彼此移动导电层和多孔构件的过程，使导电层和阳极之间的电流通过，同时保持导电 相对于多孔构件的静止层，以及停止在导电层和阳极之间的电流的供给的处理。