公开(公告)号：US5140272A

公开(公告)日：1992-08-18

申请号：US248497

申请日：1988-09-23

申请人： Shigeru Nishimatsu ,  Tatsumi Mizutani ,  Ryo Haruta ,  Kanji Tsujii ,  Chusuke Munakata ,  Shigeyuki Hosoki

发明人： Shigeru Nishimatsu ,  Tatsumi Mizutani ,  Ryo Haruta ,  Kanji Tsujii ,  Chusuke Munakata ,  Shigeyuki Hosoki

IPC分类号： G01R31/26 ,  G01N27/00 ,  G01N27/22 ,  G01N27/24 ,  G01R27/26 ,  G01R29/12 ,  G01R29/14 ,  G01R29/24 ,  H01L21/66

CPC分类号： G01R29/24 ,  G01R27/2605

摘要： A method of semiconductor surface measurement for measuring electrical characteristics of a surface of a semiconductor body is disclosed, by which an electrode, whose surface, which is opposite to the surface of a semiconductor substrate, is flat and the gap between the electrode and the surface is smaller than 0.5 .mu.m.

摘要翻译： 公开了一种半导体表面测量方法，用于测量半导体本体的表面的电特性，通过该方法，其表面与半导体衬底的表面相反的表面是平坦的，并且电极和表面之间的间隙 小于0.5亩。

公开(公告)号：US06563212B2

公开(公告)日：2003-05-13

申请号：US10046204

申请日：2002-01-16

申请人： Masanori Shibamoto ,  Masahiro Ichitani ,  Ryo Haruta ,  Katsuyuki Matsumoto ,  Junichi Arita ,  Ichiro Anjo

发明人： Masanori Shibamoto ,  Masahiro Ichitani ,  Ryo Haruta ,  Katsuyuki Matsumoto ,  Junichi Arita ,  Ichiro Anjo

IPC分类号： H01L2334

CPC分类号： H01L24/50 ,  H01L23/13 ,  H01L23/16 ,  H01L23/24 ,  H01L23/293 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/36 ,  H01L23/3672 ,  H01L23/3675 ,  H01L23/3732 ,  H01L23/3735 ,  H01L23/3736 ,  H01L23/3737 ,  H01L23/49572 ,  H01L23/49816 ,  H01L23/4985 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29144 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73269 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/0105 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/01014 ,  H01L2224/45099

摘要： A semiconductor device in which a semiconductor chip 1 is bonded by a metal bond 2 to one surface of a heat sink 4 formed of a material with a thermal expansion coefficient is close to he semiconductor chip 1, the heat sink 4 is glued to a stiffener with a silicon adhesive 5 with an elastic modulus of 10 MPa or less, a TAB tape 9 is glued to the stiffener 3 with an epoxy adhesive 6, and the semiconductor chip 1 is sealed with an epoxy sealing resin 8 with an elastic modulus of 10 GPa or more for protection from outside.

摘要翻译： 其中半导体芯片1通过金属接合2接合到由具有热膨胀系数的材料形成的散热器4的一个表面接近半导体芯片1的半导体器件，散热器4被胶合到加强件 使用弹性模量为10MPa以下的硅粘合剂5，用环氧树脂粘合剂6将TAB带9胶合到加强件3，并用环氧树脂密封树脂8密封弹性模量为10的半导体芯片1 GPa或更多用于保护外部。

公开(公告)号：US06060770A

公开(公告)日：2000-05-09

申请号：US7079

申请日：1998-01-14

申请人： Hisao Nakamura ,  Seiichi Ichihara ,  Ryosuke Kimoto ,  Hiroshi Kawakubo ,  Ryo Haruta ,  Hiroshi Koyama

发明人： Hisao Nakamura ,  Seiichi Ichihara ,  Ryosuke Kimoto ,  Hiroshi Kawakubo ,  Ryo Haruta ,  Hiroshi Koyama

IPC分类号： H01L23/28 ,  H01L21/56 ,  H01L21/60 ,  H01L23/495

CPC分类号： H01L24/50 ,  H01L23/49572 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181

摘要： The thickness of a tape carrier package having a semiconductor chip is made uniform where bonding pads are concentrated on one side of the semiconductor chip. The tape carrier package is such that dummy pads 6b are arranged on one side opposite to the side on which bonding pads (effective pins) 6a are arranged in the semiconductor chip. Dummy leads 5 are formed on an insulating tape 4. The semiconductor chip is supported with inner lead portions 5a connected to the corresponding bonding pads 6a and the inner lead portions 5a of the dummy leads 5 connected to the corresponding dummy pads 6b.

公开(公告)号：US5336638A

公开(公告)日：1994-08-09

申请号：US846828

申请日：1992-03-06

申请人： Masayuki Suzuki ,  Ryo Haruta ,  Hiroshi Shinriki ,  Masayuki Nakata

发明人： Masayuki Suzuki ,  Ryo Haruta ,  Hiroshi Shinriki ,  Masayuki Nakata

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/44

CPC分类号： H01L27/1085 ,  H01L28/40 ,  Y10S148/117

摘要： Herein disclosed is a process for manufacturing a semiconductor device, which comprises: a step of forming a first electrode composed of tantalum and tungsten over a semiconductor substrate; a step of depositing a dielectric film of tantalum oxide on the first electrode; a step of oxidizing the first electrode and the dielectric film of tantalum oxide; and a step of forming a second electrode over the dielectric film.

摘要翻译： 这里公开了一种半导体器件的制造方法，其包括：在半导体衬底上形成由钽和钨构成的第一电极的步骤; 在所述第一电极上沉积氧化钽的电介质膜的步骤; 氧化钽的第一电极和电介质膜的氧化步骤; 以及在所述电介质膜上形成第二电极的步骤。

公开(公告)号：US20080122050A1

公开(公告)日：2008-05-29

申请号：US11629703

申请日：2005-06-15

申请人： Osamu Ikeda ,  Masahide Okamoto ,  Ryo Haruta ,  Hidemasa Kagii ,  Hiroi Oka ,  Hiroyuki Nakamura

发明人： Osamu Ikeda ,  Masahide Okamoto ,  Ryo Haruta ,  Hidemasa Kagii ,  Hiroi Oka ,  Hiroyuki Nakamura

IPC分类号： H01L23/495

CPC分类号： H01L23/49562 ,  H01L23/49513 ,  H01L23/49524 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/04026 ,  H01L2224/05111 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05644 ,  H01L2224/2908 ,  H01L2224/29083 ,  H01L2224/29101 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29118 ,  H01L2224/29123 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32057 ,  H01L2224/32245 ,  H01L2224/32507 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40247 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48644 ,  H01L2224/48699 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/83805 ,  H01L2224/84801 ,  H01L2224/85205 ,  H01L2224/92247 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01063 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01032 ,  H01L2924/00012 ,  H01L2924/01022 ,  H01L2924/01026 ,  H01L2924/01083 ,  H01L2924/3512 ,  H01L2224/48744 ,  H01L2924/00015 ,  H01L2224/83205

摘要： A power semiconductor device in which a semiconductor element is die-mount-connected onto a lead frame in a Pb-free manner. In a die-mount-connection with a large difference of thermal expansion coefficient between a semiconductor element 1 and a lead frame 2, the connection is made with an intermetallic compound 200 having a melting point of 260° C. or higher or a Pb-free solder having a melting point of 260° C. or higher to 400° C. or lower, at the same time, the thermal stress produced in temperature cycles is buffered by a metal layer 100 having a melting point of 260° C. or higher. A Pb-free die-mount-connection which does not melt at the time of reflowing but have no chip crack to occur according to thermal stress can be achieved.

摘要翻译： 一种功率半导体器件，其中半导体元件以无铅方式管芯安装到引线框架上。 在半导体元件1和引线框架2之间的热膨胀系数差大的管芯安装连接中，利用熔点为260℃以上的金属间化合物200或Pb- 熔点为260℃以上且400℃以下的自由焊料，同时在温度循环中产生的热应力由熔点为260℃的金属层100缓冲，或 更高。 可以实现在回流时熔融而不会根据热应力而产生芯片裂纹的无铅模具安装连接。

公开(公告)号：US06621160B2

公开(公告)日：2003-09-16

申请号：US10046258

申请日：2002-01-16

申请人： Masanori Shibamoto ,  Masahiro Ichitani ,  Ryo Haruta ,  Katsuyuki Matsumoto ,  Junichi Arita ,  Ichiro Anjo

发明人： Masanori Shibamoto ,  Masahiro Ichitani ,  Ryo Haruta ,  Katsuyuki Matsumoto ,  Junichi Arita ,  Ichiro Anjo

IPC分类号： H01L2334

CPC分类号： H01L24/50 ,  H01L23/13 ,  H01L23/16 ,  H01L23/24 ,  H01L23/293 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/36 ,  H01L23/3672 ,  H01L23/3675 ,  H01L23/3732 ,  H01L23/3735 ,  H01L23/3736 ,  H01L23/3737 ,  H01L23/49572 ,  H01L23/49816 ,  H01L23/4985 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29144 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73269 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/0105 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/01014 ,  H01L2224/45099

摘要： A semiconductor device in which a semiconductor chip 1 is bonded by a metal bond 2 to one surface of a heat sink 4 formed of a material with a thermal expansion coefficient is close to he semiconductor chip 1, the heat sink 4 is glued to a stiffener with a silicon adhesive 5 with an elastic modulus of 10 MPa or less, a TAB tape 9 is glued to the stiffener 3 with an epoxy adhesive 6, and the semiconductor chip 1 is sealed with an epoxy sealing resin 8 with an elastic modulus of 10 GPa or more for protection from outside.

摘要翻译： 其中半导体芯片1通过金属接合2接合到由具有热膨胀系数的材料形成的散热器4的一个表面接近半导体芯片1的半导体器件，散热器4被胶合到加强件 使用弹性模量为10MPa以下的硅粘合剂5，用环氧树脂粘合剂6将TAB带9胶合到加强件3，并用环氧树脂密封树脂8密封弹性模量为10的半导体芯片1 GPa或更多用于保护外部。

公开(公告)号：US06278176B1

公开(公告)日：2001-08-21

申请号：US09545463

申请日：2000-04-07

申请人： Hisao Nakamura ,  Seiichi Ichihara ,  Ryosuke Kimoto ,  Hiroshi Kawakubo ,  Ryo Haruta ,  Hiroshi Koyama

发明人： Hisao Nakamura ,  Seiichi Ichihara ,  Ryosuke Kimoto ,  Hiroshi Kawakubo ,  Ryo Haruta ,  Hiroshi Koyama

IPC分类号： H01L2302

CPC分类号： H01L24/50 ,  H01L23/49572 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05599

摘要： The thickness of a tape carrier package having a semiconductor chip is made uniform where bonding pads are concentrated on one side of the semiconductor chip. The tape carrier package is such that dummy pads 6b are arranged on one side opposite to the side on which bonding pads (effective pins) 6a are arranged in the semiconductor chip. Dummy leads 5 are formed on an insulating tape 4. The semiconductor chip is supported with inner lead portions 5a connected to the corresponding bonding pads 6a and the inner lead portions 5a of the dummy leads 5 connected to the corresponding dummy pads 6b.

摘要翻译： 具有半导体芯片的带状载体封装的厚度在焊盘集中在半导体芯片的一侧上时是均匀的。 磁带载体封装是这样的，即，虚拟焊盘6b布置在与半导体芯片中布置有焊盘（有效引脚）6a的一侧相对的一侧上。 虚拟引线5形成在绝缘带4上。半导体芯片由连接到相应的接合焊盘6a的内部引线部分5a和连接到相应的虚设焊盘6b的虚拟引线5的内部引线部分5a支撑。

公开(公告)号：US4570175A

公开(公告)日：1986-02-11

申请号：US505377

申请日：1983-06-16

申请人： Masanobu Miyao ,  Makoto Ohkura ,  Iwao Takemoto ,  Terunori Warabisako ,  Kiichiro Mukai ,  Ryo Haruta ,  Yasushiro Nishioka ,  Shinichiro Kimura ,  Takashi Tokuyama

发明人： Masanobu Miyao ,  Makoto Ohkura ,  Iwao Takemoto ,  Terunori Warabisako ,  Kiichiro Mukai ,  Ryo Haruta ,  Yasushiro Nishioka ,  Shinichiro Kimura ,  Takashi Tokuyama

IPC分类号： H01L27/00 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L21/76264 ,  H01L27/0688 ,  H01L21/76272 ,  H01L21/76281

摘要： At least one layer of insulator film and single-crystal film are alternately stacked and deposited on a surface of a semiconductor substrate, and an impurity-doped region formed in each semiconductor film is used as a gate, source or drain of a MOS transistor.Thus, a three-dimensional semiconductor device is constructed in which MOS transistors are arranged, not only in the direction of the semiconductor substrate surface, but also in a direction perpendicular thereto.

摘要翻译： 绝缘膜和单晶膜的至少一层交替层叠并沉积在半导体衬底的表面上，并且将形成在每个半导体膜中的杂质掺杂区域用作MOS晶体管的栅极，源极或漏极。 因此，不仅在半导体衬底表面的方向上，而且在垂直于其的方向上，构成了MOS晶体管被布置的三维半导体器件。

公开(公告)号：US06844219B2

公开(公告)日：2005-01-18

申请号：US10136409

申请日：2002-05-02

申请人： Makoto Kitano ,  Akihiro Yaguchi ,  Naotaka Tanaka ,  Takeshi Terasaki ,  Ichiro Anjoh ,  Ryo Haruta ,  Asao Nishimura ,  Junichi Saeki

发明人： Makoto Kitano ,  Akihiro Yaguchi ,  Naotaka Tanaka ,  Takeshi Terasaki ,  Ichiro Anjoh ,  Ryo Haruta ,  Asao Nishimura ,  Junichi Saeki

IPC分类号： H01L23/12 ,  H01L21/60 ,  H01L23/00 ,  H01L23/02 ,  H01L23/16 ,  H01L23/31 ,  H01L23/488 ,  H01L23/495 ,  H01L23/498 ,  H05K3/34 ,  H01L21/44

CPC分类号： H01L23/16 ,  H01L23/3128 ,  H01L23/49572 ,  H01L23/49816 ,  H01L23/562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/50 ,  H01L2224/05554 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/1815 ,  H05K3/3426 ,  H05K3/3436 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor device which can improve the connection reliability of solder bumps and productivity in manufacturing. Insulating tape having wiring patterns on its surface is bonded to a lead frame. Semiconductor elements are loaded and circuit formed surfaces and sides of the semiconductor elements are sealed with sealing resin. After arrangements of individual semiconductor devices are formed, the lead frame is separated into individual metal plates to form individual semiconductor devices. Such simultaneous production of a plurality of semiconductor devices enhances productivity, and improves flatness of the insulating tape, whereby the connection reliability of solder bumps is improved.

摘要翻译： 可以提高焊料凸块的连接可靠性和制造生产率的半导体器件。 在其表面具有布线图案的绝缘带被粘合到引线框架上。 半导体元件被加载并且电路形成的表面和半导体元件的侧面被密封树脂​​密封。 在形成各个半导体器件的布置之后，将引线框架分离成单独的金属板以形成单独的半导体器件。 这种同时生产多个半导体器件提高了生产率，并且提高了绝缘带的平坦度，从而提高了焊料凸块的连接可靠性。

公开(公告)号：US06764878B2

公开(公告)日：2004-07-20

申请号：US10193289

申请日：2002-07-12

申请人： Atsushi Fujisawa ,  Takafumi Konno ,  Shingo Ohsaka ,  Ryo Haruta ,  Masahiro Ichitani

发明人： Atsushi Fujisawa ,  Takafumi Konno ,  Shingo Ohsaka ,  Ryo Haruta ,  Masahiro Ichitani

IPC分类号： H01L2148

CPC分类号： H01L24/32 ,  H01L21/565 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83194 ,  H01L2224/83385 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/07802 ,  H01L2924/10162 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/13116 ,  H01L2224/45015 ,  H01L2924/207

摘要： In a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.

摘要翻译： 在球栅阵列型半导体封装中，半导体芯片通过粘合材料安装在柔性薄膜基板的表面上。 多个凸起电极在所述基板的相对侧上排列成阵列，半导体芯片由树脂密封。 在这方面，形成绝缘层以覆盖形成在基板的表面上的导电体层图案，并且半导体芯片通过粘合材料安装在绝缘层上。 绝缘层被分成在半导体芯片下面的区域中相互不连续的多个部分。 通过该分隔绝缘层，可以防止半导体芯片与导电体层图案之间的短路，抑制包含柔性膜的基板的变形。