公开(公告)号：US11081551B2

公开(公告)日：2021-08-03

申请号：US16548144

申请日：2019-08-22

申请人： Infineon Technologies AG

发明人： Christoph Glacer ,  Stephan Pindl ,  Werner Weber ,  Sebastian Wittmann

IPC分类号： H01L21/20 ,  H01L21/36 ,  H01L29/16 ,  H01L23/532 ,  B01D71/02 ,  H01L21/02

摘要： In accordance with an embodiment, a method for producing a graphene-based sensor includes providing a carrier substrate; forming a carrier structure on the carrier substrate, wherein one or more separating structures are formed on an upper side of the carrier structure; and performing a wet chemical transfer of a graphene layer onto the upper side of the carrier structure that comprises the separating structures, where the separating structures and a tear strength of the graphene layer are matched to one another such that the graphene layer respectively tears at the separating structures during the wet chemical transfer.

公开(公告)号：US10468294B2

公开(公告)日：2019-11-05

申请号：US16077142

申请日：2017-01-31

申请人： SUNEDISON SEMICONDUCTOR LIMITED ,  Igor Peidous

发明人： Igor Peidous ,  Andrew M. Jones ,  Srikanth Kommu ,  Gang Wang ,  Jeffrey L. Libbert

IPC分类号： H01L21/20 ,  H01L21/36 ,  H01L21/30 ,  H01L21/46 ,  H01L29/04 ,  H01L31/036 ,  H01L21/762 ,  H01L21/02 ,  H01L21/28

摘要： A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and the front surface of the single crystal semiconductor handle substrate has a surface roughness of at least about 0.1 micrometers as measured according to the root mean square method over a surface area of at least 30 micrometers by 30 micrometers. The composite structure further comprises a charge trapping layer in contact with the front surface, the charge trapping layer comprising poly crystalline silicon, the poly crystalline silicon comprising grains having a plurality of crystal orientations; a dielectric layer in contact with the charge trapping layer; and a single crystal semiconductor device layer in contact with the dielectric layer.

公开(公告)号：US10242915B2

公开(公告)日：2019-03-26

申请号：US15900248

申请日：2018-02-20

申请人： Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.

发明人： Thomas Gerrer ,  Volker Cimalla ,  Taro Yoshikawa ,  Marina Preschle

IPC分类号： H01L21/20 ,  H01L21/36 ,  H01L21/78 ,  H01L21/84 ,  H01L23/373 ,  H01L23/00 ,  H01L27/12

摘要： A method for transferring at least one thin film from a first substrate to a second substrate is provided, the thin film having a first side and an opposing second side and the second side of the thin film being arranged on a first side of the first substrate, at least part of the first substrate being subsequently removed and the second substrate being brought into contact, via its first side, with the second side of the thin film, wherein a liquid is supplied to the contact surface and then at least some of the liquid is removed by rotating the thin film and the second substrate.

公开(公告)号：US10229857B2

公开(公告)日：2019-03-12

申请号：US15846968

申请日：2017-12-19

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Jeehwan Kim ,  Juntao Li ,  Devendra K. Sadana

IPC分类号： H01L21/8238 ,  H01L21/36 ,  H01L29/06 ,  H01L29/78 ,  H01L21/84 ,  H01L27/12 ,  H01L27/092 ,  H01L29/161 ,  H01L21/02 ,  H01L21/306 ,  H01L29/167 ,  H01L21/326 ,  H01L21/265 ,  H01L21/762

摘要： A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.

公开(公告)号：US09985094B2

公开(公告)日：2018-05-29

申请号：US14141720

申请日：2013-12-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Jheng-Sheng You ,  Che-Yi Lin ,  Shen-Ping Wang ,  Lieh-Chuan Chen ,  Chih-Heng Shen ,  Po-Tao Chu

IPC分类号： H01L29/66 ,  H01L21/36 ,  H01L29/06 ,  H01L29/78 ,  H01L29/40

CPC分类号： H01L29/0634 ,  H01L29/0649 ,  H01L29/407 ,  H01L29/66712 ,  H01L29/78 ,  H01L29/7802

摘要： A super junction includes a substrate and an epitaxial layer over the substrate, the epitaxial layer having a first dopant type. The super junction further includes an angled trench in the epitaxial layer, the angled trench having sidewalls disposed at an angle ranging from about 85-degrees to about 89-degrees with respect to a top surface of the epitaxial layer. The super junction further includes a doped body in the epitaxial layer surrounding the angled trench, the doped body having a second dopant type, the second dopant type opposite that of the first dopant type.

公开(公告)号：US09929011B2

公开(公告)日：2018-03-27

申请号：US15597680

申请日：2017-05-17

申请人： Ultratech, Inc.

发明人： Andrew M. Hawryluk ,  Ganesh Sundaram ,  Ritwik Bhatia

IPC分类号： H01L21/20 ,  H01L21/36 ,  H01L33/00 ,  H01L21/02 ,  H01L21/268 ,  B23K26/12 ,  H01L29/20 ,  B23K26/03 ,  B23K26/073 ,  B23K26/122 ,  C23C16/56 ,  H01L21/324 ,  C23C16/22 ,  B23K103/00

CPC分类号： H01L21/0262 ,  B23K26/034 ,  B23K26/0738 ,  B23K26/122 ,  B23K26/1224 ,  B23K2103/56 ,  C23C16/22 ,  C23C16/56 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02598 ,  H01L21/02675 ,  H01L21/02694 ,  H01L21/268 ,  H01L21/3245 ,  H01L29/2003

摘要： Method and devices are disclosed for device manufacture of gallium nitride devices by growing a gallium nitride layer on a silicon substrate using Atomic Layer Deposition (ALD) followed by rapid thermal annealing. Gallium nitride is grown directly on silicon or on a barrier layer of aluminum nitride grown on the silicon substrate. One or both layers are thermally processed by rapid thermal annealing. Preferably the ALD process use a reaction temperature below 550° C. and preferable below 350° C. The rapid thermal annealing step raises the temperature of the coating surface to a temperature ranging from 550 to 1500° C. for less than 12 msec.

公开(公告)号：US09922821B2

公开(公告)日：2018-03-20

申请号：US14671504

申请日：2015-03-27

申请人： Hitachi Kokusai Electric Inc.

发明人： Tsuyoshi Takeda

IPC分类号： H01L21/20 ,  H01L21/36 ,  H01L21/02 ,  H01L21/285 ,  C23C16/44 ,  C23C16/52 ,  C23C16/455 ,  C23C16/24 ,  C23C16/42 ,  H01L21/3205

CPC分类号： H01L21/0228 ,  C23C16/24 ,  C23C16/42 ,  C23C16/4412 ,  C23C16/45523 ,  C23C16/45557 ,  C23C16/52 ,  H01L21/02126 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/28556 ,  H01L21/32051 ,  H01L21/32053

摘要： Provided is a technique of forming a film containing a first element and a second element on a substrate by performing a cycle a predetermined number of times. The cycle includes: (a) supplying a hydro-based precursor containing the first element and a halogen-based precursor containing the second element into a process chamber accommodating a substrate to confine the hydro-based precursor and the halogen-based precursor in the process chamber; (b) maintaining a state where the hydro-based precursor and the halogen-based precursor are confined in the process chamber; and (c) exhausting the process chamber.

公开(公告)号：US09805789B2

公开(公告)日：2017-10-31

申请号：US14308786

申请日：2014-06-19

申请人： Micron Technology, Inc.

发明人： D. V. Nirmal Ramaswamy ,  Gurtej S. Sandhu

IPC分类号： H01L29/22 ,  H01L21/36 ,  G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC分类号： G11C13/0007 ,  G11C2213/55 ,  G11C2213/56 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1616

摘要： Methods, devices, and systems associated with oxide based memory are described herein. In one or more embodiments, a method of forming an oxide based memory cell includes forming a first electrode, forming a tunnel barrier, wherein a first portion of the tunnel barrier includes a first material and a second portion of the tunnel barrier includes a second material, forming an oxygen source, and forming a second electrode.

公开(公告)号：US09773815B2

公开(公告)日：2017-09-26

申请号：US15477646

申请日：2017-04-03

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Shunpei Yamazaki ,  Junichi Koezuka ,  Yukinori Shima ,  Masami Jintyou ,  Daisuke Kurosaki ,  Masataka Nakada

IPC分类号： H01L21/469 ,  H01L29/786 ,  H01L21/34 ,  H01L21/36 ,  H01L27/12 ,  H01L29/04 ,  H01L29/24 ,  H01L29/36 ,  H01L29/66

CPC分类号： H01L27/1225 ,  H01L29/045 ,  H01L29/24 ,  H01L29/36 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78621 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

摘要： In a semiconductor device including a transistor, the transistor is provided over a first insulating film, and the transistor includes an oxide semiconductor film over the first insulating film, a gate insulating film over the oxide semiconductor film, a gate electrode over the gate insulating film, a second insulating film over the oxide semiconductor film and the gate electrode, and a source and a drain electrodes electrically connected to the oxide semiconductor film. The first insulating film includes oxygen. The second insulating film includes hydrogen. The oxide semiconductor film includes a first region in contact with the gate insulating film and a second region in contact with the second insulating film. The first insulating film includes a third region overlapping with the first region and a fourth region overlapping with the second region. The impurity element concentration of the fourth region is higher than that of the third region.

公开(公告)号：US09768044B2

公开(公告)日：2017-09-19

申请号：US15138813

申请日：2016-04-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Chao Wang ,  Yu-Chang Lin ,  Li-Ting Wang ,  Tai-Chun Huang ,  Pei-Ren Jeng ,  Tze-Liang Lee

IPC分类号： H01L21/20 ,  H01L21/36 ,  H01L21/26 ,  H01L21/42 ,  H01L21/4763 ,  H01L21/00 ,  H01L21/67 ,  H01L21/268 ,  H01L21/324 ,  B23K26/00 ,  H01L21/263

CPC分类号： H01L21/67115 ,  B23K26/352 ,  H01L21/2636 ,  H01L21/268 ,  H01L21/324

摘要： A method includes performing an anneal on a wafer. The wafer includes a wafer-edge region, and an inner region encircled by the wafer-edge region. During the anneal, a first power applied on a portion of the wafer-edge region is at least lower than a second power for annealing the inner region.