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公开(公告)号：US06775907B1
公开(公告)日：2004-08-17
申请号：US09661738
申请日：2000-09-14
IPC分类号： H01K310
CPC分类号： H05K3/426 , H05K3/108 , H05K3/181 , H05K3/381 , H05K2203/1152 , H05K2203/122 , Y10T29/49155 , Y10T29/49165 , Y10T29/49167
摘要： The present invention teaches a simplified process for fabricating high density printed wiring boards using a semi-additive process. Steps required to achieve this objective include adhering an electroless plated copper commoning layer to a surface roughened dielectric substrate. Subsequently, the commoning layer is photolithographically personalized by covering the commoning layer with a resist and then uncovering predetermined areas of the aforementioned commoning layer. Consequently, the semi-additive method involves electroplating copper onto the uncovered areas of the commoning layer, thereby generating copper features and circuitry. Finally, the semi-additive process requires the stripping of the remaining photoresist, and the unplated electroless copper layer is etched in order to electronically isolate the copper features and circuitry lines.
摘要翻译： 本发明教导了使用半添加法制造高密度印刷线路板的简化方法。 实现这一目标所需的步骤包括将化学镀铜共同层粘附到表面粗糙化的电介质基底上。 随后，通过用抗蚀剂覆盖共用层，然后露出上述公共层的预定区域，通过光刻来个性化普通层。 因此，半添加方法涉及将铜电镀到公共层的未覆盖区域上，由此产生铜特征和电路。 最后，半添加工艺需要剥离剩余的光致抗蚀剂，并且蚀刻未镀覆的无电镀铜层以便电绝缘铜特征和电路线。
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公开(公告)号：US06212769B1
公开(公告)日：2001-04-10
申请号：US09343077
申请日：1999-06-29
IPC分类号： H05K330
CPC分类号： H05K3/426 , H05K3/108 , H05K3/181 , H05K3/381 , H05K2203/1152 , H05K2203/122 , Y10T29/49155 , Y10T29/49165 , Y10T29/49167
摘要： The present invention teaches a simplified process for fabricating high density printed wiring boards using a semi-additive process. A roughened copper foil is laminated to a dielectric substrate. The foil is subsequently removed from the dielectric to create a roughened, irregular surface on the dielectric substrate. Vertical angle through holes and blind holes are formed in the substrate. A uniform copper commoning layer is electrolessly plated to the roughened dielectric substrate and through holes. A photoresist is applied on the surface of the electroless plated layer and irradiated through a mask having printed circuit features. After developing the photoresist the uncovered electroless layer is electrolytically plated to create the final features and circuitry. After stripping the remaining photoresist the unplated electroless copper layer is etched to electronically isolate the copper features and circuitry lines.
摘要翻译： 本发明教导了使用半添加法制造高密度印刷线路板的简化方法。 将粗糙化的铜箔层叠到电介质基板上。 随后从电介质中去除箔以在电介质基底上产生粗糙的不规则表面。 在基板上形成垂直角通孔和盲孔。 将均匀的铜共同层无电镀在粗糙化的电介质基片和通孔上。 将光致抗蚀剂施加在化学镀层的表面上并通过具有印刷电路特征的掩模照射。 在显影光致抗蚀剂之后，未覆盖的化学镀层被电解以产生最终特征和电路。 在剥离剩余的光致抗蚀剂之后，蚀刻未镀覆的无电解铜层以电绝缘铜特征和电路线。
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公开(公告)号：US06931726B2
公开(公告)日：2005-08-23
申请号：US10436592
申请日：2003-05-13
CPC分类号： H01L23/49827 , H01L2224/16 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/3011 , H01L2924/3025 , H05K1/112 , H05K3/429 , H05K3/4602 , H05K2201/09472 , H05K2201/09509 , H05K2201/096 , H05K2201/10674 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49165
摘要： A method of making an interconnect structure having an increased chip connector pad and plated through hole density is provided. In particular, the method includes the steps of providing a substrate having at least one plated through hole therein, and positioning a first conductive layer and a second conductive layer over the at least one plated through hole on opposing surfaces of the substrate. The method includes positioning a layer of dielectric material thereon on the first conductive layer. The dielectric layer includes at least one aperture selectively positioned directly over the at least one plated through hole. The substrate further includes a metal layer, and at least a pair of conductive layers that can carry signals, and power.
摘要翻译： 提供了具有增加的芯片连接器焊盘和电镀通孔密度的互连结构的方法。 特别地，该方法包括以下步骤：提供其中具有至少一个电镀通孔的衬底，并将第一导电层和第二导电层定位在衬底的相对表面上的至少一个电镀通孔上。 该方法包括在第一导电层上定位一层电介质材料。 电介质层包括选择性地定位在至少一个电镀通孔上方的至少一个孔。 基板还包括金属层，以及至少一对可承载信号的导电层和电源。
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4.发明授权Ball limiting metal mask and tin enrichment of high melting point solder for low temperature interconnection 失效用于低温互连的高熔点焊料的极限金属掩模和锡富集
公开(公告)号：US5953623A
公开(公告)日：1999-09-14
申请号：US835690
申请日：1997-04-10
IPC分类号： H01L21/60 , H01L23/485 , H05K3/34 , H01L21/44
CPC分类号： H01L24/10 , H01L24/13 , H01L24/81 , H05K3/3436 , H01L2224/13 , H01L2224/13023 , H01L2224/13099 , H01L2224/13111 , H01L2224/13609 , H01L2224/16 , H01L2224/16225 , H01L2224/274 , H01L2224/81801 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H05K2203/0435 , H05K2203/073 , H05K3/3463 , Y02P70/613
摘要： A solder interconnection uses preferably lead-rich balls for making a low temperature chip attachment directly to any of the higher levels of packaging substrate. After a solder ball has been formed using standard processes, a ball limiting metal mask is formed using photoresist. A thin cap layer of preferably pure tin is deposited on a surface of the solder balls using a tin aqueous immersion process.
摘要翻译： 焊料互连优选地使用富铅球，以将低温芯片附接到任何更高级别的封装衬底上。 在使用标准工艺形成焊球之后，使用光致抗蚀剂形成球限制金属掩模。 使用锡水溶液浸渍法将优选纯锡的薄盖层沉积在焊球的表面上。
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公开(公告)号：US6121069A
公开(公告)日：2000-09-19
申请号：US390084
申请日：1999-09-03
CPC分类号： H01L24/10 , H01L24/13 , H01L24/81 , H05K3/3436 , H01L2224/13 , H01L2224/13023 , H01L2224/13099 , H01L2224/13111 , H01L2224/13609 , H01L2224/16 , H01L2224/16225 , H01L2224/274 , H01L2224/81801 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H05K2203/0435 , H05K2203/073 , H05K3/3463 , Y02P70/613
摘要： A solder interconnection uses preferably lead-rich balls for making a low temperature chip attachment directly to any of the higher levels of packaging substrate. After a solder ball has been formed using standard processes, a ball limiting metal mask is formed using photoresist. A thin cap layer of preferably pure tin is deposited on a surface of the solder balls using a tin aqueous immersion process.
摘要翻译： 焊料互连优选地使用富铅球，以将低温芯片附接到任何更高级别的封装衬底上。 在使用标准工艺形成焊球之后，使用光致抗蚀剂形成球限制金属掩模。 使用锡水溶液浸渍法将优选纯锡的薄盖层沉积在焊球的表面上。
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6.发明授权Method for forming electrical connection to the inner layers of a multilayer circuit board 失效用于形成与多层电路板的内层的电连接的方法
公开(公告)号：US5472735A
公开(公告)日：1995-12-05
申请号：US351819
申请日：1994-12-08
申请人： Christina M. Boyko , Richard W. Carpenter , Raymond T. Galasco , Krystyna W. Semkow , Herbert Wegener
发明人： Christina M. Boyko , Richard W. Carpenter , Raymond T. Galasco , Krystyna W. Semkow , Herbert Wegener
CPC分类号： H05K3/07 , C25F3/02 , H05K2203/1152 , Y10S204/07
摘要： The present invention relates to a method for selectively electroetching a metal from an electrical device having the steps of: immersing the electrical device in an etching solution; immersing a cathode in the etching solution; applying an etching potential to a preselected area of the metal; and maintaining a passivation potential at the metal to remain unetched. The metal to remain unetched is not electrically connected to the preselected area and the passivation potential does not equal the etching potential.The present invention further relates to a method of forming an electrical connection to the inner layers of a multilayer circuit board having a copper foil surface layer and copper containing inner layers.
摘要翻译： 本发明涉及一种从电气设备中选择性地电蚀金属的方法，其特征在于具有以下步骤：将电气设备浸入蚀刻液中; 将阴极浸入蚀刻溶液中; 将蚀刻电位施加到金属的预选区域; 并且保持在金属处的钝化电位以保持未蚀刻。 保持未蚀刻的金属不与预选区域电连接，并且钝化电势不等于蚀刻电位。 本发明还涉及一种形成与具有铜箔表面层和含铜内层的多层电路板的内层的电连接的方法。
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公开(公告)号：US4960634A
公开(公告)日：1990-10-02
申请号：US494807
申请日：1990-03-14
申请人： Christina M. Boyko , Craig N. Johnston , James R. Loomis , Carl E. Samuelson , Ricahrd A. Schumacher
发明人： Christina M. Boyko , Craig N. Johnston , James R. Loomis , Carl E. Samuelson , Ricahrd A. Schumacher
CPC分类号： H05K1/0373 , C08G59/30 , C08G59/38 , H05K1/0203 , H05K2201/0209 , H05K2203/125 , Y10T428/24917
摘要： A composition of enhanced thermal conductivity which comprises a tetrabrominated diglycidyl ether polyepoxide; and epoxy polymer having an epoxy functionality of 3.5 to 6; zinc oxide and curing agents; and use thereof.
摘要翻译： 包含四溴化二缩水甘油醚聚环氧化物的增强导热性组合物; 环氧官能度为3.5〜6的环氧聚合物; 氧化锌和固化剂; 及其用途。
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8.发明授权Process of removing holefill residue from a metallic surface of an electronic substrate 失效从电子基板的金属表面去除孔填充残渣的方法公开(公告)号：US06776852B2
公开(公告)日：2004-08-17
申请号：US10046621
申请日：2002-01-14
IPC分类号： B08B300
CPC分类号： H05K3/0094 , H05K2201/0209 , H05K2201/0959 , H05K2203/025 , H05K2203/0746 , H05K2203/0783 , H05K2203/0796 , Y10S438/906
摘要： A process of removing excess holefill material from a surface of an electronic substrate in which the holefill residue is contacted with a swelling agent followed by planarizing of the surface in the presence of an agent no stronger than a liquid having a pH of about 6 to about 8.
摘要翻译： 从电子基板的表面去除多余的孔填充材料的过程，其中孔填充残余物与溶胀剂接触，然后在不比pH大约6至大约6的液体的试剂存在下平坦化表面 8。
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公开(公告)号：US06660945B2
公开(公告)日：2003-12-09
申请号：US09978442
申请日：2001-10-16
IPC分类号： H01R1204
CPC分类号： H01L23/49827 , H01L2224/16 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/3011 , H01L2924/3025 , H05K1/112 , H05K3/429 , H05K3/4602 , H05K2201/09472 , H05K2201/09509 , H05K2201/096 , H05K2201/10674 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49165
摘要： An interconnect structure having an increased chip connector pad and plated through hole density is provided. In particular, the interconnect structure includes a substrate having at least one plated through hole therein, and a first conductive layer sealing the at least one plated through hole. The substrate includes a layer of dielectric material thereon. The dielectric layer includes at least one aperture selectively positioned directly over the at least one plated through hole. The substrate further includes a metal layer, at least a pair of conductive layers that can carry signals, and at least another pair of conductive layers that can carry power, wherein the pair of conductive layers are shielded by the metal layer and the other pair of conductive layers.
摘要翻译： 提供了具有增加的芯片连接器焊盘和电镀通孔密度的互连结构。 特别地，互连结构包括其中具有至少一个电镀通孔的基板和密封至少一个电镀通孔的第一导电层。 衬底包括其上的介电材料层。 电介质层包括选择性地定位在至少一个电镀通孔上方的至少一个孔。 基板还包括金属层，至少一对可承载信号的导电层，以及至少另一对可承载电力的导电层，其中所述一对导电层被金属层和另一对导电层屏蔽 导电层。
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10.发明授权Via fill compositions for direct attach of devices and methods for applying same 失效用于直接连接装置的填充组合物和用于施加装置的方法
公开(公告)号：US5571593A
公开(公告)日：1996-11-05
申请号：US467558
申请日：1995-06-06
申请人： Roy L. Arldt , Christina M. Boyko , Burtran J. Cayson , Richard M. Kozlowski , Joseph D. Kulesza , John M. Lauffer , Philip C. Liu , Voya R. Markovich , Issa S. Mahmoud , James F. Muska , Kostas Papathomas , Joseph G. Sabia , Richard A. Schumacher
发明人： Roy L. Arldt , Christina M. Boyko , Burtran J. Cayson , Richard M. Kozlowski , Joseph D. Kulesza , John M. Lauffer , Philip C. Liu , Voya R. Markovich , Issa S. Mahmoud , James F. Muska , Kostas Papathomas , Joseph G. Sabia , Richard A. Schumacher
IPC分类号： B32B7/04 , C08G59/40 , C08G73/00 , C08L63/00 , C09D163/00 , H01B1/20 , H01B1/22 , H01B1/24 , H05K1/09 , H05K1/11 , H05K1/16 , H05K3/00 , H05K3/40 , B32B9/00
CPC分类号： H01B1/24 , B32B7/04 , H01B1/22 , H05K1/095 , H05K1/113 , H05K1/167 , H05K3/4053 , H05K3/4069 , H01L2224/16235 , H05K1/16 , H05K2201/0347 , H05K2201/09563 , H05K2201/10734 , H05K2203/0126 , H05K2203/0191 , H05K2203/0207 , H05K2203/0278 , H05K2203/0338 , H05K2203/0763 , H05K3/0023 , H05K3/0047 , H05K3/0094 , Y10S428/901 , Y10T29/49099 , Y10T29/49144 , Y10T29/49155 , Y10T29/49165 , Y10T428/24273 , Y10T428/24331 , Y10T428/24339 , Y10T428/24826 , Y10T428/24917 , Y10T428/24926 , Y10T428/25
摘要： The present invention permits solder joints to be made directly to via and through holes without the solder being wicked into the vias or through holes, by filling plated through holes with an epoxy or cyanate fill composition. When cured and overplated, the fill composition provides support for the solder joint and provides a flat solderable surface for the inter-connection. In certain embodiments, the cured fill compositions, offer a further advantage of being conductive. The invention also relates to several novel methods for filling through holes with such fill compositions, and to resistors located in through holes and vias.
摘要翻译： 本发明允许焊接接头直接制成通孔和通孔，而不会通过用环氧树脂或氰酸盐填充组合物填充电镀通孔，焊料不会被弄脏到通孔或通孔中。 当固化和过度镀覆时，填充组合物为焊接接头提供支撑，并为相互连接提供平坦的可焊接表面。 在某些实施方案中，固化的填充组合物提供另外的导电性的优点。 本发明还涉及用这种填充组合物填充通孔的几种新方法，以及位于通孔和通孔中的电阻器。
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