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公开(公告)号:US10056308B2
公开(公告)日:2018-08-21
申请号:US15431296
申请日:2017-02-13
申请人: Intel Corporation
发明人: Paul J. Gwin
IPC分类号: H01L23/12 , H01L23/053 , H01L23/04 , H01L23/06 , G06F1/18 , H01L21/48 , H01L21/50 , H01L21/56 , H01L23/08 , H01L23/31 , H01L23/00 , H01L23/10
CPC分类号: H01L23/053 , G06F1/18 , H01L21/4803 , H01L21/481 , H01L21/4817 , H01L21/50 , H01L21/565 , H01L23/04 , H01L23/06 , H01L23/08 , H01L23/10 , H01L23/3142 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/73 , H01L24/81 , H01L2224/16113 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/01012 , H01L2924/01013 , H01L2924/01022 , H01L2924/01026 , H01L2924/01028 , H01L2924/0133 , H01L2924/06 , H01L2924/0615 , H01L2924/0635 , H01L2924/065 , H01L2924/068 , H01L2924/069 , H01L2924/0695 , H01L2924/0705 , H01L2924/10253 , H01L2924/1438 , H01L2924/1443 , H01L2924/15153 , H01L2924/16152 , H01L2924/16176 , H01L2924/1619 , H01L2924/19105 , H01L2924/00
摘要: Embodiments of the present disclosure are directed toward a molded composite enclosure for an integrated circuit (IC) assembly. In one embodiment, an enclosure for an integrated circuit (IC) assembly may include a molded lid structure having a body portion, and a side portion that extends from the body portion and forms a cavity configured to house the IC assembly, wherein the body portion and the side portion share a contiguous interior material comprising a polymer and share a contiguous exterior material comprising a metal, the contiguous interior material having an opening formed in the body portion such that the IC assembly can be thermally coupled with the contiguous exterior material through the opening. Other embodiments may be described and/or claimed.
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公开(公告)号:US20180190638A1
公开(公告)日:2018-07-05
申请号:US15479735
申请日:2017-04-05
发明人: Wei-Ming Chen , Tu-Hao Yu , Kuo-Chiang Ting , Shang-Yun Hou , Chi-Hsi Wu
IPC分类号: H01L25/00 , H01L21/48 , H01L23/498 , H01L25/18 , H01L21/56 , H01L23/00 , H01L23/367
CPC分类号: H01L25/50 , H01L21/4803 , H01L21/4817 , H01L21/4853 , H01L21/486 , H01L21/4871 , H01L21/561 , H01L21/563 , H01L21/568 , H01L21/6835 , H01L21/6836 , H01L23/3128 , H01L23/3675 , H01L23/49811 , H01L23/49827 , H01L23/49833 , H01L24/16 , H01L24/97 , H01L25/18 , H01L2221/68327 , H01L2221/68345 , H01L2221/68368 , H01L2224/16235 , H01L2224/16238 , H01L2224/95001 , H01L2924/1431 , H01L2924/1436 , H01L2924/1437 , H01L2924/1461 , H01L2924/19011 , H01L2924/19105 , H01L2924/19106
摘要: Chip on wafer on substrate structures and methods of forming are provided. The method includes attaching a first die and a second die to an interposer. The method also includes attaching a first substrate to a first surface of the first die and a first surface of the second die. The first substrate includes silicon. The first surface of the first side is opposite to the surface of the first die that is attached to the interposer, and the first surface of the second die is opposite to the surface of the second die that is attached to the interposer. The method includes bonding the interposer to a second substrate.
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公开(公告)号:US20180190570A1
公开(公告)日:2018-07-05
申请号:US15908509
申请日:2018-02-28
发明人: Fumihiko MOMOSE , Takashi SAITO
IPC分类号: H01L23/40 , H01L23/04 , H01L23/373 , H01L23/492 , H01L21/48 , C21D7/06
CPC分类号: H01L23/40 , B23K1/00 , C21D7/06 , H01L21/4817 , H01L21/4882 , H01L23/041 , H01L23/053 , H01L23/3735 , H01L23/492 , H01L23/49866 , H05K7/20
摘要: In a semiconductor device, a plurality of small depressions are formed to overlap each other in a first joining region of a back surface of a heat releasing plate. A streaky scratch or the like created on the back surface of the heat releasing plate is removed or reduced, by forming the small depressions overlapping each other on the heat releasing plate. In addition, when the small depressions are formed in the first joining region of the back surface of the heat releasing plate, the hardness of the first joining region of the back surface increases. Hence, the scratch is prevented from being created on the back surface of the heat releasing plate on which the depressions are formed to overlap each other in the first joining region of the back surface.
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公开(公告)号:US10002846B2
公开(公告)日:2018-06-19
申请号:US15792414
申请日:2017-10-24
申请人: Erick Merle Spory
发明人: Erick Merle Spory
CPC分类号: H01L24/80 , B29C64/10 , H01L21/4803 , H01L21/4817 , H01L21/50 , H01L23/04 , H01L23/10 , H01L23/20 , H01L23/26 , H01L23/49805 , H01L23/564 , H01L24/03 , H01L24/24 , H01L24/25 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/82 , H01L24/83 , H01L24/98 , H01L2224/24011 , H01L2224/24051 , H01L2224/24175 , H01L2224/24226 , H01L2224/245 , H01L2224/25171 , H01L2224/2731 , H01L2224/29124 , H01L2224/29144 , H01L2224/29147 , H01L2224/2919 , H01L2224/32225 , H01L2224/32245 , H01L2224/82102 , H01L2224/82103 , H01L2224/82214 , H01L2224/82815 , H01L2224/83192 , H01L2224/838 , H01L2224/8385 , H01L2224/92244 , H01L2224/92247 , H01L2924/00015 , H01L2924/12042 , H01L2924/14 , H01L2924/157 , H01L2924/15787 , H01L2924/15788 , H01L2924/181 , H01L2924/3656 , H01L2924/3861 , H01L2224/48 , H01L2924/00014 , H01L2924/01047 , H01L2924/01079 , H01L2924/01013 , H01L2924/01029 , H01L2924/00
摘要: A method is provided. The method includes removing an extracted die including an original ball bond from a previous packaged integrated circuit, bonding the extracted die to an interposer to create a remapped extracted die, 3D printing one or more first bond connections between one or more original bond pads of the extracted die and one or more first bond pads of the interposer, securing the remapped extracted die to a package base, and 3D printing one or more second bond connections between one or more second bond pads of the interposer and one or more package leads or downbonds of the package base. The one or more first and second bond connections conform to the shapes and surfaces of the extracted die, the interposer, and the package base.
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公开(公告)号:US09984954B2
公开(公告)日:2018-05-29
申请号:US14928206
申请日:2015-10-30
发明人: Mattias E. Dahlstrom
IPC分类号: H01L29/00 , H01L23/427 , H01L23/367 , H01L21/48 , H01L21/768 , H01L23/373 , H01L49/02 , H01L23/00 , H01L23/528 , H01L23/532 , H01L21/02 , H01L21/762 , H01L23/36 , H01L23/522
CPC分类号: H01L23/4275 , H01L21/02118 , H01L21/02164 , H01L21/0217 , H01L21/481 , H01L21/4817 , H01L21/4882 , H01L21/76224 , H01L21/76802 , H01L21/76843 , H01L21/76898 , H01L23/345 , H01L23/36 , H01L23/367 , H01L23/3675 , H01L23/3677 , H01L23/373 , H01L23/3735 , H01L23/3736 , H01L23/427 , H01L23/522 , H01L23/5226 , H01L23/528 , H01L23/5329 , H01L24/80 , H01L28/24 , H01L2924/00 , H01L2924/0002 , H01L2924/13091
摘要: A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the device. The method further includes forming a heat sink in at least one of the plurality of insulator layers and proximate to the device. The heat sink includes a reservoir of phase change material having a melting point temperature that is less than an upper limit of a design operating temperature of the chip.
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公开(公告)号:US09947560B1
公开(公告)日:2018-04-17
申请号:US15358513
申请日:2016-11-22
申请人: Xilinx, Inc.
发明人: Mohsen H. Mardi , David Tan , Gamal Refai-Ahmed
IPC分类号: H01L21/67 , H01L21/48 , H01L23/04 , H01L23/498 , H01L23/367 , H01L21/687
CPC分类号: H01L21/67121 , H01L21/4817 , H01L21/67098 , H01L21/687 , H01L21/68735 , H01L23/04 , H01L23/3675 , H01L23/49811 , H01L23/49866 , H01L2224/16225 , H01L2224/73253
摘要: An integrated circuit (IC) package, assembly tool and method for assembling an IC package are described herein. In a first example, an IC package is provided that includes a package substrate, at least a first integrated circuit (IC) die and a cover. The first integrated circuit (IC) die is mechanically and electrically coupled to the package substrate via solder connections. The cover is bonded to the package substrate. The cover encloses the first IC die and is laterally offset from a peripheral edge of the package substrate.
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公开(公告)号:US09922938B2
公开(公告)日:2018-03-20
申请号:US15257723
申请日:2016-09-06
发明人: Ming-Horng Tsai , Wei-Yu Chen , Chun-Chia Lee , Huan Wun Li
IPC分类号: H01L23/00 , H01L23/552 , H01L23/498 , H01L23/31 , H01L21/48 , H01L21/56 , H01L23/538 , H01L23/64 , H02J50/10 , H01L25/065 , H02J7/02 , H01L23/04
CPC分类号: H01L23/552 , H01L21/4817 , H01L21/485 , H01L21/4853 , H01L21/486 , H01L21/565 , H01L23/04 , H01L23/3114 , H01L23/49811 , H01L23/49827 , H01L23/49838 , H01L23/5386 , H01L23/645 , H01L24/13 , H01L24/16 , H01L24/48 , H01L25/0655 , H01L2224/13147 , H01L2224/16227 , H01L2224/16235 , H01L2224/48227 , H01L2924/00014 , H01L2924/15313 , H01L2924/181 , H01L2924/1815 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/3025 , H02J7/025 , H02J50/10 , H01L2224/45015 , H01L2924/207 , H01L2224/45099 , H01L2924/00
摘要: The present disclosure relates to a semiconductor device package which includes a carrier, an electronic component disposed on the carrier, and a package body disposed on the carrier and encapsulating the electronic component. A shield is disposed on the package body. The shield includes multiple non-magnetic conductive layers, multiple insulating layers and multiple magnetic conductive layers. At least one of the insulating layers is located between each non-magnetic conductive layer and a neighboring magnetic conductive layer.
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公开(公告)号:US20180070447A1
公开(公告)日:2018-03-08
申请号:US15797233
申请日:2017-10-30
发明人: Jim Oleson
IPC分类号: H05K1/11 , H01L23/473 , H01L23/12 , H01L25/07 , H01L23/00
CPC分类号: H05K1/113 , H01L21/4817 , H01L21/4882 , H01L23/04 , H01L23/12 , H01L23/4006 , H01L23/473 , H01L23/562 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/81 , H01L25/072 , H01L2224/0401 , H01L2224/05552 , H01L2224/05568 , H01L2224/0557 , H01L2224/131 , H01L2224/16225 , H01L2224/2919 , H01L2224/32225 , H01L2224/81193 , H01L2924/00014 , H01L2924/014 , H01L2924/10253 , H01L2924/10272 , H01L2924/10329 , H01L2924/14 , H01L2924/157 , H05B33/06 , H05B33/10
摘要: A product and method for packaging high power integrated circuits or infrared emitter arrays for operation through a wide range of temperatures, including cryogenic operation. The present invention addresses key limitations with the prior art, by providing temperature control through direct thermal conduction or active fluid flow and avoiding thermally induced stress on the integrated circuits or emitter arrays. The present invention allows for scaling of emitter arrays up to extremely large formats, which is not viable under the prior art. The present invention eliminates or otherwise reduces risks associated with vaporization of coolant within the heatsink structure.
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公开(公告)号:US20180047700A1
公开(公告)日:2018-02-15
申请号:US15792414
申请日:2017-10-24
申请人: Erick Merle Spory
发明人: Erick Merle Spory
CPC分类号: H01L24/80 , B29C64/10 , H01L21/4803 , H01L21/4817 , H01L21/50 , H01L23/04 , H01L23/10 , H01L23/20 , H01L23/26 , H01L23/49861 , H01L23/564 , H01L24/03 , H01L24/24 , H01L24/25 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/82 , H01L24/83 , H01L24/98 , H01L2224/24011 , H01L2224/24051 , H01L2224/24175 , H01L2224/24226 , H01L2224/245 , H01L2224/25171 , H01L2224/2731 , H01L2224/29124 , H01L2224/29144 , H01L2224/29147 , H01L2224/2919 , H01L2224/32225 , H01L2224/32245 , H01L2224/82102 , H01L2224/82103 , H01L2224/82214 , H01L2224/82815 , H01L2224/83192 , H01L2224/838 , H01L2224/8385 , H01L2224/92244 , H01L2224/92247 , H01L2924/00015 , H01L2924/12042 , H01L2924/14 , H01L2924/157 , H01L2924/15787 , H01L2924/15788 , H01L2924/181 , H01L2924/3656 , H01L2924/3861 , H01L2224/48 , H01L2924/00014 , H01L2924/01047 , H01L2924/01079 , H01L2924/01013 , H01L2924/01029 , H01L2924/00
摘要: A method is provided. The method includes removing an extracted die including an original ball bond from a previous packaged integrated circuit, bonding the extracted die to an interposer to create a remapped extracted die, 3D printing one or more first bond connections between one or more original bond pads of the extracted die and one or more first bond pads of the interposer, securing the remapped extracted die to a package base, and 3D printing one or more second bond connections between one or more second bond pads of the interposer and one or more package leads or downbonds of the package base. The one or more first and second bond connections conform to the shapes and surfaces of the extracted die, the interposer, and the package base.
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公开(公告)号:US09865519B2
公开(公告)日:2018-01-09
申请号:US15402329
申请日:2017-01-10
申请人: RAYTHEON COMPANY
发明人: Stephen H. Black , Adam M. Kennedy
CPC分类号: H01L23/26 , H01L21/3221 , H01L21/3225 , H01L21/4817 , H01L21/54 , H01L23/041 , H01L23/10
摘要: A system and method for forming a wafer level package. In one example, a substrate used in the wafer level package includes a surface defined by a wafer level package (WLP) region and an external region, and a layer of getter material is disposed on at least a portion of the external region. According to one embodiment, the external region comprises a saw-to-reveal (STR) region of the wafer.
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