公开(公告)号：US11727982B2

公开(公告)日：2023-08-15

申请号：US17717632

申请日：2022-04-11

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Ely Tsern ,  Craig Hampel

IPC: G11C11/15 ,  G11C11/4093 ,  G06F13/16 ,  G06F13/40 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  H01L25/065 ,  H01L25/10 ,  H01L23/00 ,  H01L25/18

CPC classification number: G11C11/4093 ,  G06F13/16 ,  G06F13/4027 ,  G06F13/4068 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C7/1006 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  H01L25/0652 ,  H01L25/105 ,  G11C7/22 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/14 ,  H01L2924/00

Abstract: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

公开(公告)号：US11720485B2

公开(公告)日：2023-08-08

申请号：US17728791

申请日：2022-04-25

Applicant: Rambus Inc.

Inventor： Thomas J. Sheffler ,  Lawrence Lai ,  Liang Peng ,  Bohuslav Rychlik

IPC: G06F12/02 ,  G11C7/22 ,  G11C8/10 ,  G11C7/10

CPC classification number: G06F12/023 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/22 ,  G11C8/10 ,  H05K999/99 ,  G06F2212/2024 ,  G11C2207/107

Abstract: A memory device having a DRAM core and a register stores first data in the register before receiving first and second memory access commands via a command interface and before receiving second data via a data interface. The memory device responds to the first memory access command by writing the first data from the register to the DRAM core and responds to the second memory access command by writing the second data from the data interface to the DRAM core.

公开(公告)号：US20230244576A1

公开(公告)日：2023-08-03

申请号：US18096812

申请日：2023-01-13

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  J. James Tringali ,  Ely Tsern

IPC: G06F11/14 ,  G11C7/20 ,  G11C14/00 ,  G06F3/06

CPC classification number: G06F11/1471 ,  G11C7/20 ,  G11C14/0018 ,  G06F3/0619 ,  G06F3/0634 ,  G06F3/0647 ,  G06F3/0685 ,  G06F2201/805 ,  G06F2201/84

Abstract: The embodiments described herein describe technologies for non-volatile memory persistence in a multi-tiered memory system including two or more memory technologies for volatile memory and non-volatile memory.

公开(公告)号：US20230236997A1

公开(公告)日：2023-07-27

申请号：US18085481

申请日：2022-12-20

Applicant: Rambus Inc.

Inventor： Chi-Ming YEUNG ,  Yoshie NAKABAYASHI ,  Thomas GIOVANNINI ,  Henry STRACOVSKY

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/1673 ,  G06F13/4022 ,  G06F13/4282 ,  G06F13/4068

Abstract: A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.

公开(公告)号：US11709736B2

公开(公告)日：2023-07-25

申请号：US17354268

申请日：2021-06-22

Applicant: Rambus Inc.

Inventor： Kenneth L. Wright ,  Frederick A. Ware

IPC: G06F11/00 ,  G06F11/14 ,  H01L23/00 ,  G06F3/06 ,  G06F13/16 ,  G06F13/40 ,  H01L25/065 ,  H01L25/10

CPC classification number: G06F11/142 ,  G06F3/0617 ,  G06F3/0634 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0683 ,  G06F11/00 ,  G06F13/1673 ,  G06F13/4068 ,  H01L24/00 ,  H01L24/17 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  G06F11/1423 ,  G06F2201/805 ,  G06F2201/82 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/4824 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/85399

Abstract: A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. The memory components can be configured to route data around defective data connections to maintain full capacity and continue to support memory transactions.

公开(公告)号：US11709525B2

公开(公告)日：2023-07-25

申请号：US17830163

申请日：2022-06-01

Applicant: Rambus Inc.

Inventor： Jun Kim ,  Pak Shing Chau ,  Wayne S. Richardson

IPC: G06F1/00 ,  G06F1/08 ,  H03L7/099 ,  H04L7/00 ,  H03L7/081 ,  H03L7/07 ,  H04L7/10 ,  G06F13/16 ,  G06F1/10

CPC classification number: G06F1/08 ,  G06F1/10 ,  G06F13/1673 ,  G06F13/1689 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/0995 ,  H04L7/0008 ,  H04L7/0033 ,  H04L7/10 ,  Y02D10/00

Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.

公开(公告)号：US20230231589A1

公开(公告)日：2023-07-20

申请号：US18096661

申请日：2023-01-13

Applicant: Rambus Inc.

Inventor： Nanyan WANG ,  Marcus VAN IERSSEL

IPC: H04B1/16

CPC classification number: H04B1/16

Abstract: An integrated circuit that includes a feedback loop to adapt receiver parameters. The feedback loop includes a receiver to sample a signal and produce a sampled signal sequence. The feedback loop also includes a first pattern counter to detect and count occurrences of a first pattern in the sampled signal sequence, and a second pattern counter to detect and count occurrences of a second pattern in the sampled signal sequence. Control circuitry coupled to the receiver adapts a parameter value of the receiver to minimize a difference between a first ratio and a second ratio. The first ratio is a target ratio. The second ratio is between a first counted number of occurrences of the first pattern in the sampled signal sequence and a second counted number of occurrences of the second pattern in the sample signal sequence.

公开(公告)号：US20230229593A1

公开(公告)日：2023-07-20

申请号：US18152642

申请日：2023-01-10

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/7203

Abstract: A hybrid memory includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive flash memory. An address buffer on the module maintains a static, random-access memory (SRAM) cache of addresses for data cached in DRAM.

公开(公告)号：US20230224101A1

公开(公告)日：2023-07-13

申请号：US18078936

申请日：2022-12-10

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Richard E. Perego ,  Craig E. Hampel

IPC: H04L1/24 ,  H04L7/00 ,  G11C7/10 ,  H04L25/02 ,  G11C29/02 ,  H04L25/12 ,  H04L27/00 ,  H04L7/10 ,  G11C7/04 ,  H04L7/033

CPC classification number: H04L1/242 ,  H04L7/0016 ,  G11C7/1084 ,  H04L25/0292 ,  G11C29/028 ,  H04L25/12 ,  G11C29/022 ,  H04L27/00 ,  G11C7/1057 ,  H04L7/10 ,  H04L7/0091 ,  G11C29/025 ,  H04L7/0087 ,  G11C7/04 ,  G11C2207/2254 ,  H04L7/033

Abstract: A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

公开(公告)号：US11687247B2

公开(公告)日：2023-06-27

申请号：US17339683

申请日：2021-06-04

Applicant: Rambus Inc.

Inventor： Aws Shallal ,  Michael Miller ,  Stephen Horn

IPC: G06F3/06 ,  G06F12/0802 ,  G06F12/14 ,  G11C14/00 ,  G11C5/04 ,  G11C11/00 ,  G06F13/16 ,  G06F11/00 ,  G11C7/10 ,  G06F11/14

CPC classification number: G06F3/0613 ,  G06F3/065 ,  G06F3/0611 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0685 ,  G06F11/00 ,  G06F12/0802 ,  G06F12/1441 ,  G06F13/1673 ,  G11C5/04 ,  G11C11/005 ,  G11C14/0009 ,  G06F11/14 ,  G06F13/1668 ,  G06F2212/1024 ,  G06F2212/205 ,  G11C7/1051 ,  Y02D10/00

Abstract: Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.