公开(公告)号：US06335493B1

公开(公告)日：2002-01-01

申请号：US09450140

申请日：1999-11-29

申请人： Michio Horiuchi ,  Shigetsugu Muramatsu

发明人： Michio Horiuchi ,  Shigetsugu Muramatsu

IPC分类号： H01R1204

CPC分类号： H05K1/112 ,  H01L23/49838 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K3/3436 ,  H05K2201/09227 ,  H05K2201/10674 ,  H01L2224/05599

摘要： A multilayer wiring board for mounting a semiconductor chip or a semiconductor device, in which the number of wiring layers in minimized, having a plurality of wiring layers, in which each of said wiring layers includes lands arranged in the form of a square lattice and wiring patterns each having one end connected to one of said lands and the other end extending outward beyond an outermost row of said lattice, said lands having a land pitch p and a land diameter d and said wiring patterns having a pattern width w and an interpattern space s, said p, d, w, and s satisfying the following relationship: p−d

摘要翻译： 一种用于安装半导体芯片或半导体器件的多层布线板，其中具有多个布线层的布线层的数量最小化，其中每个所述布线层包括以正方形格子形式布置的布点和布线 每个图案的一端连接到所述平台之一并且另一端向外延伸超过所述格子的最外面的一行，所述平台具有平台间距p和平台直径d，并且所述布线图案具有图案宽度w和图案间距 s，所述p，d，w和s满足以下关系：并且其中所述格子具有周期性无地或空位格点，所述最外行中的所有土地具有从其向外延伸的布线图案，并且所述无平面或空格 位置提供了布线图案从其向外延伸的空间，并且所述无平面或空格格点位置提供了布线图案向外延伸的空间，并且是连接 到内陆的土地。

公开(公告)号：US06271483B1

公开(公告)日：2001-08-07

申请号：US09202432

申请日：1998-12-15

申请人： Michio Horiuchi ,  Toshiaki Suyama ,  Masakuni Tokita

发明人： Michio Horiuchi ,  Toshiaki Suyama ,  Masakuni Tokita

IPC分类号： H06R909

CPC分类号： H01L23/49827 ,  H01L2223/6622 ,  H01L2924/0002 ,  H01L2924/15174 ,  H05K1/112 ,  H05K1/115 ,  H05K3/4038 ,  H05K2201/09836 ,  H05K2201/10287 ,  H05K2201/10977 ,  H05K2203/0235 ,  H01L2924/00

摘要： A wiring board has vias which penetrate the wiring board from one side to the other side. The vias are radially arranged in the direction from one side to the other side so that the interval between the vias on one side can be made smaller than the interval between the vias on the other side. In order to prevent the vias from being electrically short-circuited to each other, even if the interval between the vias provided on one side of the wiring board is extremely reduced, a plurality of vias are radially arranged in the direction from one side of the wiring board to the other side so that an interval between the vias on one side of the wiring board can be made smaller than interval of the vias on the other side. A conductor forming the core portion of the via is coated with a sheath portion made of insulating material.

摘要翻译： 布线板具有从一侧到另一侧穿过布线板的通孔。 通孔沿从一侧到另一侧的方向径向布置，使得一侧的通孔之间的间隔可以小于另一侧的通孔之间的间隔。 为了防止通孔彼此电短路，即使设置在布线板的一侧上的通孔之间的间隔极大地减小，多个通孔沿着从一侧的方向 将布线板连接到另一侧，使得布线板一侧的通路之间的间隔可以小于另一侧的通孔的间隔。 形成通孔的芯部的导体涂覆有由绝缘材料制成的护套部分。

公开(公告)号：US5602059A

公开(公告)日：1997-02-11

申请号：US525078

申请日：1995-09-08

申请人： Michio Horiuchi ,  Yoichi Harayama

发明人： Michio Horiuchi ,  Yoichi Harayama

IPC分类号： C08G77/00 ,  H01L21/60 ,  H01L23/12 ,  H01L23/14 ,  H01L23/15 ,  H01L23/24 ,  H01L23/495

CPC分类号： H01L24/50 ,  H01L23/24 ,  H01L23/49572 ,  H01L23/49582 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73269 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/3011 ,  H01L2924/351 ,  H05K2201/10734 ,  Y10T29/49004 ,  Y10T29/49146

摘要： A semiconductor device includes a flat package substrate having a main surface on which is defined a semiconductor chip mount surface portion and onto which a semiconductor chip is to be mounted and a peripheral surface portion surrounding the semiconductor chip mount surface portion. An electrically insulating elastic layer is provided on the peripheral surface portion of the flat package substrate and a wiring pattern film is provided on an exposed main surface of the elastic layer. The wiring pattern film includes a base insulting film and wiring patterns which are formed on the base insulation film, each wiring pattern having a first end connected to an external connection terminal and a second end connected to the semiconductor chip. The semiconductor chip is sealed with a resin by potting.

摘要翻译： 半导体器件包括具有主表面的扁平封装基板，半导体芯片安装表面部分被限定在半导体芯片安装表面部分上，并且半导体芯片将被安装在该平坦封装基板上以及围绕半导体芯片安装表面部分的外围表面部分。 在平坦封装基板的周面部分设置有电绝缘的弹性层，并且在弹性层的暴露的主表面上设置布线图案膜。 布线图案膜包括基底绝缘膜和形成在基底绝缘膜上的布线图案，每个布线图案具有连接到外部连接端子的第一端和连接到半导体芯片的第二端。 半导体芯片通过灌封用树脂密封。

公开(公告)号：US5464950A

公开(公告)日：1995-11-07

申请号：US115767

申请日：1993-09-03

申请人： Michio Horiuchi ,  Yoichi Harayama ,  Koishiro Hayashi

发明人： Michio Horiuchi ,  Yoichi Harayama ,  Koishiro Hayashi

IPC分类号： H01L21/48 ,  H05K1/03 ,  H05K1/09 ,  H05K1/11 ,  H05K3/24 ,  H05K3/38 ,  H05K3/40 ,  H05K3/46 ,  H05K1/00

CPC分类号： H01L21/4857 ,  H01L21/4867 ,  H05K3/4061 ,  H05K1/0306 ,  H05K1/092 ,  H05K1/115 ,  H05K2201/0317 ,  H05K2201/09781 ,  H05K2201/09909 ,  H05K2203/025 ,  H05K2203/1383 ,  H05K3/245 ,  H05K3/388 ,  H05K3/4611 ,  H05K3/4629

摘要： An aluminum nitride circuit board includes an aluminum nitride ceramic body. An inner conductor metal which is to be used as a wiring material is formed in the aluminum nitride ceramic body. The inner conductor metal is mainly made of copper, a melting point of which is lower than a firing temperature of the aluminum nitride ceramic. A layer mainly made of a periodic table IVa group metal or compound, such as titanium, zirconium, or hafnium, is formed in an interface between the aluminum nitride ceramic body and the inner conductor metal.

摘要翻译： 氮化铝电路板包括氮化铝陶瓷体。 在氮化铝陶瓷体中形成用作布线材料的内导体金属。 内导体金属主要由铜制成，其熔点低于氮化铝陶瓷的烧制温度。 在氮化铝陶瓷体和内部导体金属的界面上形成主要由周期表IVa族金属或化合物如钛，锆或铪构成的层。

公开(公告)号：US4827082A

公开(公告)日：1989-05-02

申请号：US207218

申请日：1988-06-16

申请人： Michio Horiuchi ,  Kihou Mizushima

发明人： Michio Horiuchi ,  Kihou Mizushima

IPC分类号： H01L23/08 ,  H01L23/02 ,  H01L23/15

CPC分类号： H01L23/15 ,  H01L24/29 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83805 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/09701 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/16195

摘要： A ceramic package includes a high thermal conductive ceramic substrate (AlN or SiC sintered substrate) on which a semiconductor element is mounted, and a mullite sintered frame having metal conductive paths therein and joined to the substrate.

摘要翻译： 陶瓷封装包括其上安装有半导体元件的高导热陶瓷衬底（AlN或SiC烧结衬底）和在其中具有金属导电路径并且连接到衬底的莫来石烧结框架。

公开(公告)号：US20110220404A1

公开(公告)日：2011-09-15

申请号：US13032071

申请日：2011-02-22

申请人： Tomoo Yamasaki ,  Michio Horiuchi

发明人： Tomoo Yamasaki ,  Michio Horiuchi

IPC分类号： H05K1/11 ,  H05K3/10 ,  H01K3/10

CPC分类号： H05K3/4602 ,  H01L21/486 ,  H01L23/142 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15724 ,  H05K3/4644 ,  H05K2201/10378 ,  H05K2203/0315 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/0401

摘要： A wiring substrate includes a composite substrate including an oxidized aluminum substrate portion in which a large number of penetration conductors penetrating in a thickness direction are provided, and a frame-like aluminum substrate portion provided around the oxidized aluminum substrate portion, and a wiring layer of n layers (n is an integer of 1 or more) connected to the penetration conductors.

摘要翻译： 布线基板包括复合基板，该复合基板包括设置有大量贯穿厚度方向的贯通导体的氧化铝基板部分和设置在氧化铝基板部分周围的框状铝基板部分，以及布线层 连接到穿透导体的n层（n为1以上的整数）。

公开(公告)号：US06731010B2

公开(公告)日：2004-05-04

申请号：US09922872

申请日：2001-08-06

申请人： Michio Horiuchi ,  Takashi Kurihara

发明人： Michio Horiuchi ,  Takashi Kurihara

IPC分类号： H01L2302

CPC分类号： H01L23/02 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/49816 ,  H01L24/48 ,  H01L2221/68377 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85001 ,  H01L2224/85399 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device which reduces and simultaneously achieves a uniform mounting height, does not require complicated steps for mounting individual chips, improves the manufacturing yield, achieves a uniform height of the semiconductor device without being affected by the variation in thickness of the chips, and enables execution of electrical tests all together and a process for production of the same, wherein a semiconductor chip is housed, with its active surface facing upward, in a through hole of a printed circuit board provided with an interconnection pattern on its top surface, electrode terminals of the active surface are connected to the interconnection pattern by bonding wires, a sealing resin layer seals the bonding wires and semiconductor chip together and fixes the semiconductor chip in the through hole, and the bottom surface of the printed circuit board, the downward facing back surface of the semiconductor chip, and the bottom surface of the sealing resin layer are finished to the same flat surface by grinding and polishing.

摘要翻译： 减少并同时实现均匀安装高度的半导体器件不需要用于安装单个芯片的复杂步骤，提高制造成品率，在不受芯片厚度变化的影响的情况下实现半导体器件的均匀高度，并且使得 一起执行电气测试及其制造方法，其中将半导体芯片的活性表面朝上放置在其顶表面上具有互连图案的印刷电路板的通孔中，电极端子 的活性表面通过接合线连接到互连图案，密封树脂层将接合线和半导体芯片一起密封在一起，并将半导体芯片固定在通孔中，并且印刷电路板的底表面向下的背面 半导体芯片的表面和密封树脂层的底面为f 通过磨削和抛光成为相同的平面。

公开(公告)号：US06522017B2

公开(公告)日：2003-02-18

申请号：US09797887

申请日：2001-03-02

申请人： Michio Horiuchi ,  Takashi Kurihara

发明人： Michio Horiuchi ,  Takashi Kurihara

IPC分类号： H01L2348

CPC分类号： H01L24/81 ,  H01L21/563 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/29 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/181 ,  H05K1/112 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/10674 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/0665

摘要： Wiring board having a wiring layer to which electronic components are electrically connected, in through-holes closed at one of the ends thereof by the wiring layer are formed at predetermined positions of the wiring board, and a low melting point metal for electrically connecting the wiring layer to the electronic components is filled into the through-holes, and a semiconductor device using the same. The production methods of the wiring board and the semiconductor device are also disclosed.

摘要翻译： 在布线基板的规定位置形成具有电连接电路的布线层的布线层，其布线基板的一个端部封闭的贯通孔，布线基板的电气连接用的低熔点金属 电子部件的层被填充到通孔中，以及使用其的半导体器件。 还公开了布线板和半导体器件的制造方法。

公开(公告)号：US06452115B2

公开(公告)日：2002-09-17

申请号：US09781302

申请日：2001-02-13

申请人： Michio Horiuchi ,  Eiji Yoda ,  Chiaki Takubo

发明人： Michio Horiuchi ,  Eiji Yoda ,  Chiaki Takubo

IPC分类号： H51R909

CPC分类号： H05K1/112 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0298 ,  H05K2201/09227 ,  H05K2201/10734

摘要： A multi-layer circuit board for mounting an electronic part such as a semiconductor chip having as many pins as 40×40 pins arranged as an array on the side of the mounting surface or a semiconductor device has a plurality of layers, each layer disposed one above another and containing lands arranged as an array disposed at an angle to the edge of the mounting surface. On each layer a plurality of the lands have connected thereto circuits extending from the lands to the edge of the mounting surface, and also lands not connected to circuits. Those lands not connected to circuits are connected with via holes to orther layers. The numbers (n−2) of lands and the position of lands connected to circuits on a layer is defined where n is the smallest integer that satisfies the equation m≧(k+1) wherein m={(land pitch)×(n−1)−(land diameter)−(space between patterns)}÷(pattern width+space between patterns) and k=&agr;(n−1)+(n−2).

摘要翻译： 用于安装诸如半导体芯片的电子部件的多层电路板，具有作为阵列布置成安装面侧面的40×40引脚的半导体芯片或半导体器件的半导体芯片具有多层，每层设置在另一层上 并且包括布置成与安装表面的边缘成一定角度设置的阵列。 在每个层上，多个焊盘已经连接到从焊盘延伸到安装表面的边缘的电路，并且还没有连接到电路。 未连接到电路的那些焊盘与通孔连接到其他层。 定义了土地的数量（n-2）和连接到层上的电路的土地的位置，其中n是满足等式m> =（k + 1）的最小整数，其中

公开(公告)号：US06256207B1

公开(公告)日：2001-07-03

申请号：US09347909

申请日：1999-07-06

申请人： Michio Horiuchi ,  Shigetsugu Muramatsu

发明人： Michio Horiuchi ,  Shigetsugu Muramatsu

IPC分类号： H05K118

CPC分类号： H01L23/3114 ,  H01L21/563 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05599

摘要： A chip-sized semiconductor device includes a semiconductor element having a plurality of electrodes and a plurality of connecting pads electrically connected to the respective electrodes. A connecting board includes a base substrate having a first surface and a second surface, a plurality of connecting holes extending from the first surface to the second surface, a plurality of lands formed on the first surface to close the respective connecting holes, the lands being arranged in conformity with positions of the connecting pads of the semiconductor element, each of the connecting pads having a surface area smaller than that of the land. The semiconductor element is mounted on the connecting board in such a manner that the connecting pads of the semiconductor element are electrically connected to the respective lands of the connecting board by means of a plurality of bumps, respectively. A plurality of external connecting terminals on the second surface of the base substrate to be in contact with the respective lands through the respective connectings holes.

摘要翻译： 芯片尺寸的半导体器件包括具有多个电极的半导体元件和电连接到各个电极的多个连接焊盘。 连接板包括具有第一表面和第二表面的基底基板，从第一表面延伸到第二表面的多个连接孔，形成在第一表面上以闭合各个连接孔的多个连接孔， 与半导体元件的连接焊盘的位置一致地布置，每个连接焊盘的表面积小于焊盘的表面积。 半导体元件以这样的方式安装在连接板上，使得半导体元件的连接焊盘分别通过多个凸块电连接到连接板的相应焊盘。 多个外部连接端子，位于基底基板的第二表面上，以通过相应的连接孔与相应的凸台相接触。